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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Zelalem Aweke96c0bab2021-07-11 18:39:39 -05002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/console.h>
Ambroise Vincent9660dc12019-07-12 13:47:03 +010014#include <lib/debugfs.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/extensions/ras.h>
johpow019d134022021-06-16 17:57:28 -050016#if ENABLE_RME
17#include <lib/gpt_rme/gpt_rme.h>
18#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000021#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000023#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024
Dan Handley9df48042015-03-19 18:58:55 +000025/*
26 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000027 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000028 */
29static entry_point_info_t bl32_image_ep_info;
30static entry_point_info_t bl33_image_ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050031#if ENABLE_RME
32static entry_point_info_t rmm_image_ep_info;
33#endif
Dan Handley9df48042015-03-19 18:58:55 +000034
Soby Mathew7823d9e2018-10-14 08:13:44 +010035#if !RESET_TO_BL31
Soby Mathewaf14b462018-06-01 16:53:38 +010036/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010037 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
Soby Mathewaf14b462018-06-01 16:53:38 +010038 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
39 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010040CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
Soby Mathew7823d9e2018-10-14 08:13:44 +010041#endif
Dan Handley9df48042015-03-19 18:58:55 +000042
43/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000044#pragma weak bl31_early_platform_setup2
Dan Handley9df48042015-03-19 18:58:55 +000045#pragma weak bl31_platform_setup
46#pragma weak bl31_plat_arch_setup
47#pragma weak bl31_plat_get_next_image_ep_info
Dan Handley9df48042015-03-19 18:58:55 +000048
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010049#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
Soby Mathew7823d9e2018-10-14 08:13:44 +010050 BL31_START, \
51 BL31_END - BL31_START, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050052 MT_MEMORY | MT_RW | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010053#if RECLAIM_INIT_CODE
54IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010055IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
David Horstmann8f15ca32020-10-14 15:17:49 +010056IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010057
58#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
59 ~(PAGE_SIZE - 1))
David Horstmann8f15ca32020-10-14 15:17:49 +010060#define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
61 ~(PAGE_SIZE - 1))
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010062
63#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
64 BL_INIT_CODE_BASE, \
65 BL_INIT_CODE_END \
66 - BL_INIT_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050067 MT_CODE | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010068#endif
Dan Handley9df48042015-03-19 18:58:55 +000069
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060070#if SEPARATE_NOBITS_REGION
71#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
72 BL31_NOBITS_BASE, \
73 BL31_NOBITS_LIMIT \
74 - BL31_NOBITS_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050075 MT_MEMORY | MT_RW | EL3_PAS)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060076
77#endif
Dan Handley9df48042015-03-19 18:58:55 +000078/*******************************************************************************
79 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000080 * security state specified. BL33 corresponds to the non-secure image type
81 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000082 * if the image does not exist.
83 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020084struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Dan Handley9df48042015-03-19 18:58:55 +000085{
86 entry_point_info_t *next_image_info;
87
88 assert(sec_state_is_valid(type));
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050089 if (type == NON_SECURE) {
90 next_image_info = &bl33_image_ep_info;
91 }
92#if ENABLE_RME
93 else if (type == REALM) {
94 next_image_info = &rmm_image_ep_info;
95 }
96#endif
97 else {
98 next_image_info = &bl32_image_ep_info;
99 }
100
Dan Handley9df48042015-03-19 18:58:55 +0000101 /*
102 * None of the images on the ARM development platforms can have 0x0
103 * as the entrypoint
104 */
105 if (next_image_info->pc)
106 return next_image_info;
107 else
108 return NULL;
109}
110
111/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000112 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +0000113 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
John Tsichritzisd653d332018-09-14 10:34:57 +0100114 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
Dan Handley9df48042015-03-19 18:58:55 +0000115 * done before the MMU is initialized so that the memory layout can be used
116 * while creating page tables. BL2 has flushed this information to memory, so
117 * we are guaranteed to pick up good data.
118 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100119void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000120 uintptr_t hw_config, void *plat_params_from_bl2)
Dan Handley9df48042015-03-19 18:58:55 +0000121{
122 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100123 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000124
125#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +0000126 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +0000127 assert(from_bl2 == NULL);
128 assert(plat_params_from_bl2 == NULL);
129
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100130# ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +0000131 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +0000132 SET_PARAM_HEAD(&bl32_image_ep_info,
133 PARAM_EP,
134 VERSION_1,
135 0);
136 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
137 bl32_image_ep_info.pc = BL32_BASE;
138 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Manish Pandey18a0c3e2020-07-16 00:38:59 +0100139
140#if defined(SPD_spmd)
141 /* SPM (hafnium in secure world) expects SPM Core manifest base address
142 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
143 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
144 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
145 * keep it in the last page.
146 */
147 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
148 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
149#endif
150
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100151# endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000152
Juan Castillo7d199412015-12-14 09:35:25 +0000153 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +0000154 SET_PARAM_HEAD(&bl33_image_ep_info,
155 PARAM_EP,
156 VERSION_1,
157 0);
158 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000159 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000160 * is located and the entry state information
161 */
162 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100163
Dan Handley9df48042015-03-19 18:58:55 +0000164 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
165 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
166
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100167#else /* RESET_TO_BL31 */
168
Dan Handley9df48042015-03-19 18:58:55 +0000169 /*
170 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000171 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000172 * In release builds, it's not used.
173 */
174 assert(((unsigned long long)plat_params_from_bl2) ==
175 ARM_BL31_PLAT_PARAM_VAL);
176
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100177 /*
178 * Check params passed from BL2 should not be NULL,
179 */
180 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
181 assert(params_from_bl2 != NULL);
182 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
183 assert(params_from_bl2->h.version >= VERSION_2);
184
185 bl_params_node_t *bl_params = params_from_bl2->head;
186
187 /*
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500188 * Copy BL33, BL32 and RMM (if present), entry point information.
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100189 * They are stored in Secure RAM, in BL2's address space.
190 */
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100191 while (bl_params != NULL) {
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500192 if (bl_params->image_id == BL32_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100193 bl32_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500194 }
195#if ENABLE_RME
196 else if (bl_params->image_id == RMM_IMAGE_ID) {
197 rmm_image_ep_info = *bl_params->ep_info;
198 }
199#endif
200 else if (bl_params->image_id == BL33_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100201 bl33_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500202 }
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100203
204 bl_params = bl_params->next_params_info;
205 }
206
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100207 if (bl33_image_ep_info.pc == 0U)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100208 panic();
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500209#if ENABLE_RME
210 if (rmm_image_ep_info.pc == 0U)
211 panic();
212#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100213#endif /* RESET_TO_BL31 */
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000214
215# if ARM_LINUX_KERNEL_AS_BL33
216 /*
217 * According to the file ``Documentation/arm64/booting.txt`` of the
218 * Linux kernel tree, Linux expects the physical address of the device
219 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
220 * must be 0.
Olivier Deprez735ac782021-10-20 15:17:07 +0200221 * Repurpose the option to load Hafnium hypervisor in the normal world.
222 * It expects its manifest address in x0. This is essentially the linux
223 * dts (passed to the primary VM) by adding 'hypervisor' and chosen
224 * nodes specifying the Hypervisor configuration.
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000225 */
Zelalem Aweke1e8e3fd2021-07-26 21:39:05 -0500226#if RESET_TO_BL31
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000227 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
Zelalem Aweke1e8e3fd2021-07-26 21:39:05 -0500228#else
229 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config;
230#endif
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000231 bl33_image_ep_info.args.arg1 = 0U;
232 bl33_image_ep_info.args.arg2 = 0U;
233 bl33_image_ep_info.args.arg3 = 0U;
234# endif
Dan Handley9df48042015-03-19 18:58:55 +0000235}
236
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000237void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
238 u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000239{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000240 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Dan Handley9df48042015-03-19 18:58:55 +0000241
242 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000243 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000244 * No need for locks as no other CPU is active.
245 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000246 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100247
Dan Handley9df48042015-03-19 18:58:55 +0000248 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000249 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100250 * Earlier bootloader stages might already do this (e.g. Trusted
251 * Firmware's BL1 does it) but we can't assume so. There is no harm in
252 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000253 * Platform specific PSCI code will enable coherency for other
254 * clusters.
255 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000256 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000257}
258
259/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000260 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000261 ******************************************************************************/
262void arm_bl31_platform_setup(void)
263{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000264 /* Initialize the GIC driver, cpu and distributor interfaces */
265 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000266 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000267
268#if RESET_TO_BL31
269 /*
270 * Do initial security configuration to allow DRAM/device access
271 * (if earlier BL has not already done so).
272 */
273 plat_arm_security_setup();
274
Roberto Vargas550eb082018-01-05 16:00:05 +0000275#if defined(PLAT_ARM_MEM_PROT_ADDR)
276 arm_nor_psci_do_dyn_mem_protect();
277#endif /* PLAT_ARM_MEM_PROT_ADDR */
278
Dan Handley9df48042015-03-19 18:58:55 +0000279#endif /* RESET_TO_BL31 */
280
281 /* Enable and initialize the System level generic timer */
282 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100283 CNTCR_FCREQ(0U) | CNTCR_EN);
Dan Handley9df48042015-03-19 18:58:55 +0000284
285 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100286 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000287
288 /* Initialize power controller before setting up topology */
289 plat_arm_pwrc_setup();
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000290
291#if RAS_EXTENSION
292 ras_init();
293#endif
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100294
295#if USE_DEBUGFS
296 debugfs_init();
297#endif /* USE_DEBUGFS */
Dan Handley9df48042015-03-19 18:58:55 +0000298}
299
Soby Mathew2fd66be2015-12-09 11:38:43 +0000300/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000301 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000302 * standard platforms
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100303 * Perform BL31 platform setup
Soby Mathew2fd66be2015-12-09 11:38:43 +0000304 ******************************************************************************/
305void arm_bl31_plat_runtime_setup(void)
306{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100307 console_switch_state(CONSOLE_FLAG_RUNTIME);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100308
Soby Mathew2fd66be2015-12-09 11:38:43 +0000309 /* Initialize the runtime console */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100310 arm_console_runtime_init();
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000311
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100312#if RECLAIM_INIT_CODE
313 arm_free_init_memory();
314#endif
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000315
316#if PLAT_RO_XLAT_TABLES
317 arm_xlat_make_tables_readonly();
318#endif
Soby Mathew2fd66be2015-12-09 11:38:43 +0000319}
320
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100321#if RECLAIM_INIT_CODE
322/*
David Horstmann8f15ca32020-10-14 15:17:49 +0100323 * Make memory for image boot time code RW to reclaim it as stack for the
324 * secondary cores, or RO where it cannot be reclaimed:
325 *
326 * |-------- INIT SECTION --------|
327 * -----------------------------------------
328 * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
329 * | STACK | STACK | STACK | SPACE |
330 * -----------------------------------------
331 * <-------------------> <------>
332 * MAKE RW AND XN MAKE
333 * FOR STACKS RO AND XN
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100334 */
335void arm_free_init_memory(void)
336{
David Horstmann8f15ca32020-10-14 15:17:49 +0100337 int ret = 0;
338
339 if (BL_STACKS_END < BL_INIT_CODE_END) {
340 /* Reclaim some of the init section as stack if possible. */
341 if (BL_INIT_CODE_BASE < BL_STACKS_END) {
342 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
343 BL_STACKS_END - BL_INIT_CODE_BASE,
344 MT_RW_DATA);
345 }
346 /* Make the rest of the init section read-only. */
347 ret |= xlat_change_mem_attributes(BL_STACKS_END,
348 BL_INIT_CODE_END - BL_STACKS_END,
349 MT_RO_DATA);
350 } else {
351 /* The stacks cover the init section, so reclaim it all. */
352 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100353 BL_INIT_CODE_END - BL_INIT_CODE_BASE,
354 MT_RW_DATA);
David Horstmann8f15ca32020-10-14 15:17:49 +0100355 }
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100356
357 if (ret != 0) {
358 ERROR("Could not reclaim initialization code");
359 panic();
360 }
361}
362#endif
363
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100364void __init bl31_platform_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000365{
366 arm_bl31_platform_setup();
367}
368
Soby Mathew2fd66be2015-12-09 11:38:43 +0000369void bl31_plat_runtime_setup(void)
370{
371 arm_bl31_plat_runtime_setup();
372}
373
Dan Handley9df48042015-03-19 18:58:55 +0000374/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100375 * Perform the very early platform specific architectural setup shared between
376 * ARM standard platforms. This only does basic initialization. Later
377 * architectural setup (bl31_arch_setup()) does not do anything platform
378 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000379 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100380void __init arm_bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000381{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100382 const mmap_region_t bl_regions[] = {
383 MAP_BL31_TOTAL,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500384#if ENABLE_RME
385 ARM_MAP_L0_GPT_REGION,
386#endif
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100387#if RECLAIM_INIT_CODE
388 MAP_BL_INIT_CODE,
389#endif
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600390#if SEPARATE_NOBITS_REGION
391 MAP_BL31_NOBITS,
392#endif
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100393 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100394#if USE_ROMLIB
395 ARM_MAP_ROMLIB_CODE,
396 ARM_MAP_ROMLIB_DATA,
397#endif
Dan Handley9df48042015-03-19 18:58:55 +0000398#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100399 ARM_MAP_BL_COHERENT_RAM,
Dan Handley9df48042015-03-19 18:58:55 +0000400#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100401 {0}
402 };
403
Roberto Vargas344ff022018-10-19 16:44:18 +0100404 setup_page_tables(bl_regions, plat_arm_get_mmap());
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100405
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100406 enable_mmu_el3(0);
Roberto Vargase3adc372018-05-23 09:27:06 +0100407
johpow019d134022021-06-16 17:57:28 -0500408#if ENABLE_RME
409 /*
410 * Initialise Granule Protection library and enable GPC for the primary
411 * processor. The tables have already been initialized by a previous BL
412 * stage, so there is no need to provide any PAS here. This function
413 * sets up pointers to those tables.
414 */
415 if (gpt_runtime_init() < 0) {
416 ERROR("gpt_runtime_init() failed!\n");
417 panic();
418 }
419#endif /* ENABLE_RME */
420
Roberto Vargase3adc372018-05-23 09:27:06 +0100421 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000422}
423
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100424void __init bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000425{
426 arm_bl31_plat_arch_setup();
427}