Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 8 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/bl_common.h> |
| 10 | #include <common/debug.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 11 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 12 | #include <cpu_macros.S> |
| 13 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 15 | /* --------------------------------------------- |
| 16 | * Disable L1 data cache and unified L2 cache |
| 17 | * --------------------------------------------- |
| 18 | */ |
| 19 | func cortex_a57_disable_dcache |
| 20 | mrs x1, sctlr_el3 |
| 21 | bic x1, x1, #SCTLR_C_BIT |
| 22 | msr sctlr_el3, x1 |
| 23 | isb |
| 24 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 25 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 26 | |
| 27 | /* --------------------------------------------- |
| 28 | * Disable all types of L2 prefetches. |
| 29 | * --------------------------------------------- |
| 30 | */ |
| 31 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 32 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 33 | orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 34 | mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK |
| 35 | orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 36 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 37 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 38 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 39 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 40 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 41 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 42 | |
| 43 | /* --------------------------------------------- |
| 44 | * Disable intra-cluster coherency |
| 45 | * --------------------------------------------- |
| 46 | */ |
| 47 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 48 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 49 | bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 50 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 51 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 52 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 53 | |
| 54 | /* --------------------------------------------- |
| 55 | * Disable debug interfaces |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | func cortex_a57_disable_ext_debug |
| 59 | mov x0, #1 |
| 60 | msr osdlr_el1, x0 |
| 61 | isb |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 62 | #if ERRATA_A57_817169 |
| 63 | /* |
| 64 | * Invalidate any TLB address |
| 65 | */ |
| 66 | mov x0, #0 |
| 67 | tlbi vae3, x0 |
| 68 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 69 | dsb sy |
| 70 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 71 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 72 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 73 | /* -------------------------------------------------- |
| 74 | * Errata Workaround for Cortex A57 Errata #806969. |
| 75 | * This applies only to revision r0p0 of Cortex A57. |
| 76 | * Inputs: |
| 77 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 78 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 79 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 80 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 81 | func errata_a57_806969_wa |
| 82 | /* |
| 83 | * Compare x0 against revision r0p0 |
| 84 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 85 | mov x17, x30 |
| 86 | bl check_errata_806969 |
| 87 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 88 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 89 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 90 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 91 | 1: |
| 92 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 93 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 94 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 95 | func check_errata_806969 |
| 96 | mov x1, #0x00 |
| 97 | b cpu_rev_var_ls |
| 98 | endfunc check_errata_806969 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 99 | |
| 100 | /* --------------------------------------------------- |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 101 | * Errata Workaround for Cortex A57 Errata #813419. |
| 102 | * This applies only to revision r0p0 of Cortex A57. |
| 103 | * --------------------------------------------------- |
| 104 | */ |
| 105 | func check_errata_813419 |
| 106 | /* |
| 107 | * Even though this is only needed for revision r0p0, it |
| 108 | * is always applied due to limitations of the current |
| 109 | * errata framework. |
| 110 | */ |
| 111 | mov x0, #ERRATA_APPLIES |
| 112 | ret |
| 113 | endfunc check_errata_813419 |
| 114 | |
| 115 | /* --------------------------------------------------- |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 116 | * Errata Workaround for Cortex A57 Errata #813420. |
| 117 | * This applies only to revision r0p0 of Cortex A57. |
| 118 | * Inputs: |
| 119 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 120 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 121 | * --------------------------------------------------- |
| 122 | */ |
| 123 | func errata_a57_813420_wa |
| 124 | /* |
| 125 | * Compare x0 against revision r0p0 |
| 126 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 127 | mov x17, x30 |
| 128 | bl check_errata_813420 |
| 129 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 130 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 131 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI |
| 132 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 133 | 1: |
| 134 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 135 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 136 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 137 | func check_errata_813420 |
| 138 | mov x1, #0x00 |
| 139 | b cpu_rev_var_ls |
| 140 | endfunc check_errata_813420 |
| 141 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 142 | /* --------------------------------------------------- |
| 143 | * Errata Workaround for Cortex A57 Errata #814670. |
| 144 | * This applies only to revision r0p0 of Cortex A57. |
| 145 | * Inputs: |
| 146 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 147 | * Shall clobber: x0-x17 |
| 148 | * --------------------------------------------------- |
| 149 | */ |
| 150 | func errata_a57_814670_wa |
| 151 | /* |
| 152 | * Compare x0 against revision r0p0 |
| 153 | */ |
| 154 | mov x17, x30 |
| 155 | bl check_errata_814670 |
| 156 | cbz x0, 1f |
| 157 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 158 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION |
| 159 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
| 160 | isb |
| 161 | 1: |
| 162 | ret x17 |
| 163 | endfunc errata_a57_814670_wa |
| 164 | |
| 165 | func check_errata_814670 |
| 166 | mov x1, #0x00 |
| 167 | b cpu_rev_var_ls |
| 168 | endfunc check_errata_814670 |
| 169 | |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 170 | /* ---------------------------------------------------- |
| 171 | * Errata Workaround for Cortex A57 Errata #817169. |
| 172 | * This applies only to revision <= r0p1 of Cortex A57. |
| 173 | * ---------------------------------------------------- |
| 174 | */ |
| 175 | func check_errata_817169 |
| 176 | /* |
| 177 | * Even though this is only needed for revision <= r0p1, it |
| 178 | * is always applied because of the low cost of the workaround. |
| 179 | */ |
| 180 | mov x0, #ERRATA_APPLIES |
| 181 | ret |
| 182 | endfunc check_errata_817169 |
| 183 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 184 | /* -------------------------------------------------------------------- |
| 185 | * Disable the over-read from the LDNP instruction. |
| 186 | * |
| 187 | * This applies to all revisions <= r1p2. The performance degradation |
| 188 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 189 | * |
| 190 | * Inputs: |
| 191 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 192 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 193 | * --------------------------------------------------------------------- |
| 194 | */ |
| 195 | func a57_disable_ldnp_overread |
| 196 | /* |
| 197 | * Compare x0 against revision r1p2 |
| 198 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 199 | mov x17, x30 |
| 200 | bl check_errata_disable_ldnp_overread |
| 201 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 202 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 203 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD |
| 204 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 205 | 1: |
| 206 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 207 | endfunc a57_disable_ldnp_overread |
| 208 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 209 | func check_errata_disable_ldnp_overread |
| 210 | mov x1, #0x12 |
| 211 | b cpu_rev_var_ls |
| 212 | endfunc check_errata_disable_ldnp_overread |
| 213 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 214 | /* --------------------------------------------------- |
| 215 | * Errata Workaround for Cortex A57 Errata #826974. |
| 216 | * This applies only to revision <= r1p1 of Cortex A57. |
| 217 | * Inputs: |
| 218 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 219 | * Shall clobber: x0-x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 220 | * --------------------------------------------------- |
| 221 | */ |
| 222 | func errata_a57_826974_wa |
| 223 | /* |
| 224 | * Compare x0 against revision r1p1 |
| 225 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 226 | mov x17, x30 |
| 227 | bl check_errata_826974 |
| 228 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 229 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 230 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB |
| 231 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 232 | 1: |
| 233 | ret x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 234 | endfunc errata_a57_826974_wa |
| 235 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 236 | func check_errata_826974 |
| 237 | mov x1, #0x11 |
| 238 | b cpu_rev_var_ls |
| 239 | endfunc check_errata_826974 |
| 240 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 241 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 242 | * Errata Workaround for Cortex A57 Errata #826977. |
| 243 | * This applies only to revision <= r1p1 of Cortex A57. |
| 244 | * Inputs: |
| 245 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 246 | * Shall clobber: x0-x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 247 | * --------------------------------------------------- |
| 248 | */ |
| 249 | func errata_a57_826977_wa |
| 250 | /* |
| 251 | * Compare x0 against revision r1p1 |
| 252 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 253 | mov x17, x30 |
| 254 | bl check_errata_826977 |
| 255 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 256 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 257 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE |
| 258 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 259 | 1: |
| 260 | ret x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 261 | endfunc errata_a57_826977_wa |
| 262 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 263 | func check_errata_826977 |
| 264 | mov x1, #0x11 |
| 265 | b cpu_rev_var_ls |
| 266 | endfunc check_errata_826977 |
| 267 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 268 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 269 | * Errata Workaround for Cortex A57 Errata #828024. |
| 270 | * This applies only to revision <= r1p1 of Cortex A57. |
| 271 | * Inputs: |
| 272 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 273 | * Shall clobber: x0-x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 274 | * --------------------------------------------------- |
| 275 | */ |
| 276 | func errata_a57_828024_wa |
| 277 | /* |
| 278 | * Compare x0 against revision r1p1 |
| 279 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 280 | mov x17, x30 |
| 281 | bl check_errata_828024 |
| 282 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 283 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 284 | /* |
| 285 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 286 | * instructions here because the resulting bitmask doesn't fit in a |
| 287 | * 16-bit value so it cannot be encoded in a single instruction. |
| 288 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 289 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 290 | orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ |
| 291 | CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) |
| 292 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 293 | 1: |
| 294 | ret x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 295 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 296 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 297 | func check_errata_828024 |
| 298 | mov x1, #0x11 |
| 299 | b cpu_rev_var_ls |
| 300 | endfunc check_errata_828024 |
| 301 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 302 | /* --------------------------------------------------- |
| 303 | * Errata Workaround for Cortex A57 Errata #829520. |
| 304 | * This applies only to revision <= r1p2 of Cortex A57. |
| 305 | * Inputs: |
| 306 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 307 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 308 | * --------------------------------------------------- |
| 309 | */ |
| 310 | func errata_a57_829520_wa |
| 311 | /* |
| 312 | * Compare x0 against revision r1p2 |
| 313 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 314 | mov x17, x30 |
| 315 | bl check_errata_829520 |
| 316 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 317 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 318 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR |
| 319 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 320 | 1: |
| 321 | ret x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 322 | endfunc errata_a57_829520_wa |
| 323 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 324 | func check_errata_829520 |
| 325 | mov x1, #0x12 |
| 326 | b cpu_rev_var_ls |
| 327 | endfunc check_errata_829520 |
| 328 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 329 | /* --------------------------------------------------- |
| 330 | * Errata Workaround for Cortex A57 Errata #833471. |
| 331 | * This applies only to revision <= r1p2 of Cortex A57. |
| 332 | * Inputs: |
| 333 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 334 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 335 | * --------------------------------------------------- |
| 336 | */ |
| 337 | func errata_a57_833471_wa |
| 338 | /* |
| 339 | * Compare x0 against revision r1p2 |
| 340 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 341 | mov x17, x30 |
| 342 | bl check_errata_833471 |
| 343 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 344 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 345 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH |
| 346 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 347 | 1: |
| 348 | ret x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 349 | endfunc errata_a57_833471_wa |
| 350 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 351 | func check_errata_833471 |
| 352 | mov x1, #0x12 |
| 353 | b cpu_rev_var_ls |
| 354 | endfunc check_errata_833471 |
| 355 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 356 | /* -------------------------------------------------- |
| 357 | * Errata Workaround for Cortex A57 Errata #859972. |
| 358 | * This applies only to revision <= r1p3 of Cortex A57. |
| 359 | * Inputs: |
| 360 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 361 | * Shall clobber: |
| 362 | * -------------------------------------------------- |
| 363 | */ |
| 364 | func errata_a57_859972_wa |
| 365 | mov x17, x30 |
| 366 | bl check_errata_859972 |
| 367 | cbz x0, 1f |
| 368 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 369 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
| 370 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
| 371 | 1: |
| 372 | ret x17 |
| 373 | endfunc errata_a57_859972_wa |
| 374 | |
| 375 | func check_errata_859972 |
| 376 | mov x1, #0x13 |
| 377 | b cpu_rev_var_ls |
| 378 | endfunc check_errata_859972 |
| 379 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 380 | func check_errata_cve_2017_5715 |
| 381 | #if WORKAROUND_CVE_2017_5715 |
| 382 | mov x0, #ERRATA_APPLIES |
| 383 | #else |
| 384 | mov x0, #ERRATA_MISSING |
| 385 | #endif |
| 386 | ret |
| 387 | endfunc check_errata_cve_2017_5715 |
| 388 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 389 | func check_errata_cve_2018_3639 |
| 390 | #if WORKAROUND_CVE_2018_3639 |
| 391 | mov x0, #ERRATA_APPLIES |
| 392 | #else |
| 393 | mov x0, #ERRATA_MISSING |
| 394 | #endif |
| 395 | ret |
| 396 | endfunc check_errata_cve_2018_3639 |
| 397 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 398 | /* ------------------------------------------------- |
| 399 | * The CPU Ops reset function for Cortex-A57. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 400 | * Shall clobber: x0-x19 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 401 | * ------------------------------------------------- |
| 402 | */ |
| 403 | func cortex_a57_reset_func |
| 404 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 405 | bl cpu_get_rev_var |
| 406 | mov x18, x0 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 407 | |
| 408 | #if ERRATA_A57_806969 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 409 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 410 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 411 | #endif |
| 412 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 413 | #if ERRATA_A57_813420 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 414 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 415 | bl errata_a57_813420_wa |
| 416 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 417 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 418 | #if ERRATA_A57_814670 |
| 419 | mov x0, x18 |
| 420 | bl errata_a57_814670_wa |
| 421 | #endif |
| 422 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 423 | #if A57_DISABLE_NON_TEMPORAL_HINT |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 424 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 425 | bl a57_disable_ldnp_overread |
| 426 | #endif |
| 427 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 428 | #if ERRATA_A57_826974 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 429 | mov x0, x18 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 430 | bl errata_a57_826974_wa |
| 431 | #endif |
| 432 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 433 | #if ERRATA_A57_826977 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 434 | mov x0, x18 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 435 | bl errata_a57_826977_wa |
| 436 | #endif |
| 437 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 438 | #if ERRATA_A57_828024 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 439 | mov x0, x18 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 440 | bl errata_a57_828024_wa |
| 441 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 442 | |
| 443 | #if ERRATA_A57_829520 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 444 | mov x0, x18 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 445 | bl errata_a57_829520_wa |
| 446 | #endif |
| 447 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 448 | #if ERRATA_A57_833471 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 449 | mov x0, x18 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 450 | bl errata_a57_833471_wa |
| 451 | #endif |
| 452 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 453 | #if ERRATA_A57_859972 |
| 454 | mov x0, x18 |
| 455 | bl errata_a57_859972_wa |
| 456 | #endif |
| 457 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 458 | #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 |
Dimitris Papastamos | 570c06a | 2018-04-06 15:29:34 +0100 | [diff] [blame] | 459 | adr x0, wa_cve_2017_5715_mmu_vbar |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 460 | msr vbar_el3, x0 |
Dimitris Papastamos | bb0aa39 | 2018-06-07 13:20:19 +0100 | [diff] [blame] | 461 | /* isb will be performed before returning from this function */ |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 462 | #endif |
| 463 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 464 | #if WORKAROUND_CVE_2018_3639 |
| 465 | mrs x0, CORTEX_A57_CPUACTLR_EL1 |
| 466 | orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE |
| 467 | msr CORTEX_A57_CPUACTLR_EL1, x0 |
| 468 | isb |
| 469 | dsb sy |
| 470 | #endif |
| 471 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 472 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 473 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 474 | * --------------------------------------------- |
| 475 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 476 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 477 | orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 478 | msr CORTEX_A57_ECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 479 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 480 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 481 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 482 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 483 | /* ---------------------------------------------------- |
| 484 | * The CPU Ops core power down function for Cortex-A57. |
| 485 | * ---------------------------------------------------- |
| 486 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 487 | func cortex_a57_core_pwr_dwn |
| 488 | mov x18, x30 |
| 489 | |
| 490 | /* --------------------------------------------- |
| 491 | * Turn off caches. |
| 492 | * --------------------------------------------- |
| 493 | */ |
| 494 | bl cortex_a57_disable_dcache |
| 495 | |
| 496 | /* --------------------------------------------- |
| 497 | * Disable the L2 prefetches. |
| 498 | * --------------------------------------------- |
| 499 | */ |
| 500 | bl cortex_a57_disable_l2_prefetch |
| 501 | |
| 502 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 503 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 504 | * --------------------------------------------- |
| 505 | */ |
| 506 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 507 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 508 | |
| 509 | /* --------------------------------------------- |
| 510 | * Come out of intra cluster coherency |
| 511 | * --------------------------------------------- |
| 512 | */ |
| 513 | bl cortex_a57_disable_smp |
| 514 | |
| 515 | /* --------------------------------------------- |
| 516 | * Force the debug interfaces to be quiescent |
| 517 | * --------------------------------------------- |
| 518 | */ |
| 519 | mov x30, x18 |
| 520 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 521 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 522 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 523 | /* ------------------------------------------------------- |
| 524 | * The CPU Ops cluster power down function for Cortex-A57. |
| 525 | * ------------------------------------------------------- |
| 526 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 527 | func cortex_a57_cluster_pwr_dwn |
| 528 | mov x18, x30 |
| 529 | |
| 530 | /* --------------------------------------------- |
| 531 | * Turn off caches. |
| 532 | * --------------------------------------------- |
| 533 | */ |
| 534 | bl cortex_a57_disable_dcache |
| 535 | |
| 536 | /* --------------------------------------------- |
| 537 | * Disable the L2 prefetches. |
| 538 | * --------------------------------------------- |
| 539 | */ |
| 540 | bl cortex_a57_disable_l2_prefetch |
| 541 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 542 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 543 | /* ------------------------------------------------- |
| 544 | * Flush the L1 caches. |
| 545 | * ------------------------------------------------- |
| 546 | */ |
| 547 | mov x0, #DCCISW |
| 548 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 549 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 550 | /* --------------------------------------------- |
| 551 | * Disable the optional ACP. |
| 552 | * --------------------------------------------- |
| 553 | */ |
| 554 | bl plat_disable_acp |
| 555 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 556 | /* ------------------------------------------------- |
| 557 | * Flush the L2 caches. |
| 558 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 559 | */ |
| 560 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 561 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 562 | |
| 563 | /* --------------------------------------------- |
| 564 | * Come out of intra cluster coherency |
| 565 | * --------------------------------------------- |
| 566 | */ |
| 567 | bl cortex_a57_disable_smp |
| 568 | |
| 569 | /* --------------------------------------------- |
| 570 | * Force the debug interfaces to be quiescent |
| 571 | * --------------------------------------------- |
| 572 | */ |
| 573 | mov x30, x18 |
| 574 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 575 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 576 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 577 | #if REPORT_ERRATA |
| 578 | /* |
| 579 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 580 | */ |
| 581 | func cortex_a57_errata_report |
| 582 | stp x8, x30, [sp, #-16]! |
| 583 | |
| 584 | bl cpu_get_rev_var |
| 585 | mov x8, x0 |
| 586 | |
| 587 | /* |
| 588 | * Report all errata. The revision-variant information is passed to |
| 589 | * checking functions of each errata. |
| 590 | */ |
| 591 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 592 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 593 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 594 | report_errata ERRATA_A57_814670, cortex_a57, 814670 |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 595 | report_errata ERRATA_A57_817169, cortex_a57, 817169 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 596 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 597 | disable_ldnp_overread |
| 598 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 599 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 600 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 601 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 602 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 603 | report_errata ERRATA_A57_859972, cortex_a57, 859972 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 604 | report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 605 | report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 606 | |
| 607 | ldp x8, x30, [sp], #16 |
| 608 | ret |
| 609 | endfunc cortex_a57_errata_report |
| 610 | #endif |
| 611 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 612 | /* --------------------------------------------- |
| 613 | * This function provides cortex_a57 specific |
| 614 | * register information for crash reporting. |
| 615 | * It needs to return with x6 pointing to |
| 616 | * a list of register names in ascii and |
| 617 | * x8 - x15 having values of registers to be |
| 618 | * reported. |
| 619 | * --------------------------------------------- |
| 620 | */ |
| 621 | .section .rodata.cortex_a57_regs, "aS" |
| 622 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 623 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 624 | |
| 625 | func cortex_a57_cpu_reg_dump |
| 626 | adr x6, cortex_a57_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 627 | mrs x8, CORTEX_A57_ECTLR_EL1 |
| 628 | mrs x9, CORTEX_A57_MERRSR_EL1 |
| 629 | mrs x10, CORTEX_A57_L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 630 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 631 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 632 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 633 | declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 634 | cortex_a57_reset_func, \ |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 635 | check_errata_cve_2017_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 636 | CPU_NO_EXTRA2_FUNC, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 637 | cortex_a57_core_pwr_dwn, \ |
| 638 | cortex_a57_cluster_pwr_dwn |