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git01.mediatek.com / filogic / atf / 141c2995a0c0c01122b046a1d8fee9faef61b10f / . / plat / ti / k3 / common / plat_common.mk
blob: 23efa31945e04ca5e8fb98b19815f7b9ea30303e [file] [log] [blame]
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]1#
Dave Gerlach33689952022-02-11 13:57:19 -0600[diff] [blame]2# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# We don't use BL1 or BL2, so BL31 is the first image to execute
8RESET_TO_BL31 := 1
9# Only one core starts up at first
10COLD_BOOT_SINGLE_CPU := 1
11# We can choose where a core starts executing
12PROGRAMMABLE_RESET_ADDRESS:= 1
13
Nishanth Menonb7a47ae2020-12-10 22:17:58 -0600[diff] [blame]14# ARM coherency is managed in hardware
Andrew F. Davisf86a5de2019-04-25 14:02:33 -0400[diff] [blame]15WARMBOOT_ENABLE_DCACHE_EARLY := 1
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]16
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]17# A53 erratum for SoC. (enable them all)
18ERRATA_A53_826319 := 1
19ERRATA_A53_835769 := 1
20ERRATA_A53_836870 := 1
21ERRATA_A53_843419 := 1
22ERRATA_A53_855873 := 1
Nishanth Menon3a285f02020-12-10 16:49:42 -0600[diff] [blame]23ERRATA_A53_1530924 := 1
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]24
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]25# A72 Erratum for SoC
26ERRATA_A72_859971 := 1
Nishanth Menonb4251f12020-12-10 16:57:35 -0600[diff] [blame]27ERRATA_A72_1319367 := 1
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]28
Andrew F. Davis8d19f1c2019-05-14 15:38:11 -0500[diff] [blame]29CRASH_REPORTING := 1
Andrew F. Davis8d19f1c2019-05-14 15:38:11 -0500[diff] [blame]30
Andrew F. Davis26e89122019-01-22 14:16:03 -0600[diff] [blame]31# Split out RO data into a non-executable section
32SEPARATE_CODE_AND_RODATA := 1
33
Andrew F. Davis4ab7e012019-01-04 16:04:01 -0600[diff] [blame]34# Generate a Position Independent Executable
35ENABLE_PIE := 1
36
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]37TI_16550_MDR_QUIRK := 1
38$(eval $(call add_define,TI_16550_MDR_QUIRK))
39
Jan Kiszkab99c0782020-05-20 07:35:48 +0200[diff] [blame]40K3_USART := 0
41$(eval $(call add_define,K3_USART))
42
Andreas Dannenberg5e6d1402019-01-14 13:20:15 -0600[diff] [blame]43# Allow customizing the UART baud rate
44K3_USART_BAUD := 115200
45$(eval $(call add_define,K3_USART_BAUD))
46
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]47# Libraries
48include lib/xlat_tables_v2/xlat_tables.mk
49
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]50PLAT_INCLUDES += \
51 -I${PLAT_PATH}/include \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]52 -I${PLAT_PATH}/common/drivers/sec_proxy \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]53 -I${PLAT_PATH}/common/drivers/ti_sci \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]54
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]55K3_CONSOLE_SOURCES += \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]56 drivers/ti/uart/aarch64/16550_console.S \
57 ${PLAT_PATH}/common/k3_console.c \
58
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]59# Include GICv3 driver files
60include drivers/arm/gic/v3/gicv3.mk
61
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]62K3_GIC_SOURCES += \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]63 ${GICV3_SOURCES} \
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]64 plat/common/plat_gicv3.c \
65 ${PLAT_PATH}/common/k3_gicv3.c \
66
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]67K3_PSCI_SOURCES += \
68 plat/common/plat_psci_common.c \
69 ${PLAT_PATH}/common/k3_psci.c \
70
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]71K3_SEC_PROXY_SOURCES += \
72 ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
73
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]74K3_TI_SCI_SOURCES += \
75 ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
76
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]77PLAT_BL_COMMON_SOURCES += \
78 lib/cpus/aarch64/cortex_a53.S \
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]79 lib/cpus/aarch64/cortex_a72.S \
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]80 ${XLAT_TABLES_LIB_SRCS} \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]81 ${K3_CONSOLE_SOURCES} \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]82
83BL31_SOURCES += \
84 ${PLAT_PATH}/common/k3_bl31_setup.c \
Benjamin Fairf807a342016-10-18 14:32:06 -0500[diff] [blame]85 ${PLAT_PATH}/common/k3_helpers.S \
Benjamin Fair42eea872016-10-14 01:13:47 +0000[diff] [blame]86 ${PLAT_PATH}/common/k3_topology.c \
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]87 ${K3_GIC_SOURCES} \
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]88 ${K3_PSCI_SOURCES} \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]89 ${K3_SEC_PROXY_SOURCES} \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]90 ${K3_TI_SCI_SOURCES} \