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git01.mediatek.com / filogic / atf / b7a47ae82f9dd558b5ea8ab080a88f727d7adb07 / . / plat / ti / k3 / common / plat_common.mk
blob: ab7366b7e2b4b54004b2d45edf9c43db327f8010 [file] [log] [blame]
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]1#
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000[diff] [blame]2# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# We don't use BL1 or BL2, so BL31 is the first image to execute
8RESET_TO_BL31 := 1
9# Only one core starts up at first
10COLD_BOOT_SINGLE_CPU := 1
11# We can choose where a core starts executing
12PROGRAMMABLE_RESET_ADDRESS:= 1
13
Nishanth Menonb7a47ae2020-12-10 22:17:58 -0600[diff] [blame^]14# ARM coherency is managed in hardware
Andrew F. Davisf86a5de2019-04-25 14:02:33 -0400[diff] [blame]15WARMBOOT_ENABLE_DCACHE_EARLY := 1
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]16
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]17# A53 erratum for SoC. (enable them all)
18ERRATA_A53_826319 := 1
19ERRATA_A53_835769 := 1
20ERRATA_A53_836870 := 1
21ERRATA_A53_843419 := 1
22ERRATA_A53_855873 := 1
Nishanth Menon3a285f02020-12-10 16:49:42 -0600[diff] [blame]23ERRATA_A53_1530924 := 1
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]24
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]25# A72 Erratum for SoC
26ERRATA_A72_859971 := 1
Nishanth Menonb4251f12020-12-10 16:57:35 -0600[diff] [blame]27ERRATA_A72_1319367 := 1
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]28
Andrew F. Davis8d19f1c2019-05-14 15:38:11 -0500[diff] [blame]29CRASH_REPORTING := 1
30HANDLE_EA_EL3_FIRST := 1
31
Andrew F. Davis26e89122019-01-22 14:16:03 -0600[diff] [blame]32# Split out RO data into a non-executable section
33SEPARATE_CODE_AND_RODATA := 1
34
Andrew F. Davis4ab7e012019-01-04 16:04:01 -0600[diff] [blame]35# Generate a Position Independent Executable
36ENABLE_PIE := 1
37
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]38TI_16550_MDR_QUIRK := 1
39$(eval $(call add_define,TI_16550_MDR_QUIRK))
40
Jan Kiszkab99c0782020-05-20 07:35:48 +0200[diff] [blame]41K3_USART := 0
42$(eval $(call add_define,K3_USART))
43
Andreas Dannenberg5e6d1402019-01-14 13:20:15 -0600[diff] [blame]44# Allow customizing the UART baud rate
45K3_USART_BAUD := 115200
46$(eval $(call add_define,K3_USART_BAUD))
47
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]48# Libraries
49include lib/xlat_tables_v2/xlat_tables.mk
50
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]51PLAT_INCLUDES += \
52 -I${PLAT_PATH}/include \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]53 -I${PLAT_PATH}/common/drivers/sec_proxy \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]54 -I${PLAT_PATH}/common/drivers/ti_sci \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]55
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]56K3_CONSOLE_SOURCES += \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]57 drivers/ti/uart/aarch64/16550_console.S \
58 ${PLAT_PATH}/common/k3_console.c \
59
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]60# Include GICv3 driver files
61include drivers/arm/gic/v3/gicv3.mk
62
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]63K3_GIC_SOURCES += \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]64 ${GICV3_SOURCES} \
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]65 plat/common/plat_gicv3.c \
66 ${PLAT_PATH}/common/k3_gicv3.c \
67
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]68K3_PSCI_SOURCES += \
69 plat/common/plat_psci_common.c \
70 ${PLAT_PATH}/common/k3_psci.c \
71
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]72K3_SEC_PROXY_SOURCES += \
73 ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
74
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]75K3_TI_SCI_SOURCES += \
76 ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
77
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]78PLAT_BL_COMMON_SOURCES += \
79 lib/cpus/aarch64/cortex_a53.S \
Nishanth Menon4f9ef162018-06-22 06:36:29 -0500[diff] [blame]80 lib/cpus/aarch64/cortex_a72.S \
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]81 ${XLAT_TABLES_LIB_SRCS} \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]82 ${K3_CONSOLE_SOURCES} \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]83
84BL31_SOURCES += \
85 ${PLAT_PATH}/common/k3_bl31_setup.c \
Benjamin Fairf807a342016-10-18 14:32:06 -0500[diff] [blame]86 ${PLAT_PATH}/common/k3_helpers.S \
Benjamin Fair42eea872016-10-14 01:13:47 +0000[diff] [blame]87 ${PLAT_PATH}/common/k3_topology.c \
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]88 ${K3_GIC_SOURCES} \
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]89 ${K3_PSCI_SOURCES} \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]90 ${K3_SEC_PROXY_SOURCES} \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]91 ${K3_TI_SCI_SOURCES} \