Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Jit Loon Lim | ffa06e7 | 2023-07-07 17:15:26 +0800 | [diff] [blame] | 7 | #ifndef N5X_SOCFPGA_CLOCKMANAGER_H |
| 8 | #define N5X_SOCFPGA_CLOCKMANAGER_H |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 9 | |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 10 | |
| 11 | /* MACRO DEFINITION */ |
| 12 | #define SOCFPGA_GLOBAL_TIMER 0xffd01000 |
| 13 | #define SOCFPGA_GLOBAL_TIMER_EN 0x3 |
| 14 | |
| 15 | #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) |
| 16 | #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 |
| 17 | #define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8) |
| 18 | #define CLKMGR_PLLDIV_FDIV_OFFSET 8 |
| 19 | #define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0) |
| 20 | #define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0 |
| 21 | #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) |
| 22 | #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 |
| 23 | |
Jit Loon Lim | a9fca83 | 2022-12-22 21:52:36 +0800 | [diff] [blame] | 24 | #define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) |
| 25 | #define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 26 | #define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8) |
| 27 | #define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8 |
| 28 | #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) |
| 29 | #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 |
| 30 | #define CLKMGR_CLKSRC_MASK GENMASK(18, 16) |
| 31 | #define CLKMGR_CLKSRC_OFFSET 16 |
| 32 | #define CLKMGR_NOCDIV_DIVIDER_MASK GENMASK(1, 0) |
| 33 | #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 |
| 34 | |
| 35 | #define CLKMGR_INTOSC_HZ 400000000 |
| 36 | #define CLKMGR_VCO_PSRC_EOSC1 0 |
| 37 | #define CLKMGR_VCO_PSRC_INTOSC 1 |
| 38 | #define CLKMGR_VCO_PSRC_F2S 2 |
| 39 | #define CLKMGR_CLKSRC_MAIN 0 |
| 40 | #define CLKMGR_CLKSRC_PER 1 |
| 41 | |
| 42 | #define CLKMGR_N5X_BASE 0xffd10000 |
| 43 | #define CLKMGR_MAINPLL_NOCCLK 0x40 |
| 44 | #define CLKMGR_MAINPLL_NOCDIV 0x44 |
| 45 | #define CLKMGR_MAINPLL_PLLGLOB 0x48 |
| 46 | #define CLKMGR_MAINPLL_PLLOUTDIV 0x54 |
| 47 | #define CLKMGR_MAINPLL_PLLDIV 0x50 |
| 48 | #define CLKMGR_PERPLL_PLLGLOB 0x9c |
| 49 | #define CLKMGR_PERPLL_PLLDIV 0xa4 |
| 50 | #define CLKMGR_PERPLL_PLLOUTDIV 0xa8 |
| 51 | |
| 52 | /* FUNCTION DEFINITION */ |
| 53 | uint64_t clk_get_pll_output_hz(void); |
| 54 | uint64_t get_l4_clk(void); |
| 55 | uint32_t get_clk_freq(uint32_t psrc_reg); |
Jit Loon Lim | a9fca83 | 2022-12-22 21:52:36 +0800 | [diff] [blame] | 56 | uint32_t get_mpu_clk(void); |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 57 | uint32_t get_cpu_clk(void); |
Jit Loon Lim | ffa06e7 | 2023-07-07 17:15:26 +0800 | [diff] [blame] | 58 | uint32_t get_mpu_periph_clk(void); |
Sieu Mun Tang | f48707a | 2022-06-23 18:05:02 +0800 | [diff] [blame] | 59 | |
Jit Loon Lim | ffa06e7 | 2023-07-07 17:15:26 +0800 | [diff] [blame] | 60 | #endif /* N5X_SOCFPGA_CLOCKMANAGER_H */ |