fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
diff --git a/plat/intel/soc/n5x/include/n5x_clock_manager.h b/plat/intel/soc/n5x/include/n5x_clock_manager.h
index 6e2b978..14a5717 100644
--- a/plat/intel/soc/n5x/include/n5x_clock_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_clock_manager.h
@@ -22,6 +22,8 @@
#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
+#define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
+#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
#define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
#define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8
#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
@@ -52,6 +54,7 @@
uint64_t clk_get_pll_output_hz(void);
uint64_t get_l4_clk(void);
uint32_t get_clk_freq(uint32_t psrc_reg);
+uint32_t get_mpu_clk(void);
uint32_t get_cpu_clk(void);
#endif