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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Soby Mathewd0194872016-04-29 19:01:30 +010036#include <smcc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010037#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010038#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
40/*******************************************************************************
41 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
42 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010043int psci_cpu_on(u_register_t target_cpu,
44 uintptr_t entrypoint,
45 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
47{
48 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000049 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
51 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010052 rc = psci_validate_mpidr(target_cpu);
53 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010054 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010055
Soby Mathewf1f97a12015-07-15 12:13:26 +010056 /* Validate the entry point and get the entry_point_info */
57 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000058 if (rc != PSCI_E_SUCCESS)
59 return rc;
60
Soby Mathew8595b872015-01-06 15:36:38 +000061 /*
Soby Mathew981487a2015-07-13 14:10:57 +010062 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000063 * levels need to be turned on
64 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010065 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010066}
67
68unsigned int psci_version(void)
69{
70 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
71}
72
73int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010074 uintptr_t entrypoint,
75 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076{
77 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010078 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000079 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010080 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
81 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010082
Soby Mathew981487a2015-07-13 14:10:57 +010083 /* Validate the power_state parameter */
84 rc = psci_validate_power_state(power_state, &state_info);
85 if (rc != PSCI_E_SUCCESS) {
86 assert(rc == PSCI_E_INVALID_PARAMS);
87 return rc;
88 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010089
Soby Mathew981487a2015-07-13 14:10:57 +010090 /*
91 * Get the value of the state type bit from the power state parameter.
92 */
93 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010094
Soby Mathew981487a2015-07-13 14:10:57 +010095 /* Sanity check the requested suspend levels */
Soby Mathew24ab34f2016-05-03 17:11:42 +010096 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
Soby Mathew981487a2015-07-13 14:10:57 +010097 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010098
Soby Mathew981487a2015-07-13 14:10:57 +010099 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
100
101 /* Fast path for CPU standby.*/
102 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
103 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100104 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100105
Soby Mathew981487a2015-07-13 14:10:57 +0100106 /*
107 * Set the state of the CPU power domain to the platform
108 * specific retention state and enter the standby state.
109 */
110 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
111 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100112
113#if ENABLE_PSCI_STAT
114 /*
115 * Capture time-stamp before CPU standby
116 * No cache maintenance is needed as caches
117 * are ON through out the CPU standby operation.
118 */
119 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
120 PMF_NO_CACHE_MAINT);
121#endif
122
Soby Mathew981487a2015-07-13 14:10:57 +0100123 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100124
Soby Mathew981487a2015-07-13 14:10:57 +0100125 /* Upon exit from standby, set the state back to RUN. */
126 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100127
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100128#if ENABLE_PSCI_STAT
129 /* Capture time-stamp after CPU standby */
130 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
131 PMF_NO_CACHE_MAINT);
132
133 /* Update PSCI stats */
134 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info,
135 PMF_NO_CACHE_MAINT);
136#endif
137
Soby Mathew74e52a72014-10-02 16:56:51 +0100138 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000139 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140
Achin Gupta42c52802014-05-09 19:32:25 +0100141 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100142 * If a power down state has been requested, we need to verify entry
143 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000144 */
Soby Mathew981487a2015-07-13 14:10:57 +0100145 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100146 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100147 if (rc != PSCI_E_SUCCESS)
148 return rc;
149 }
Soby Mathewf5121572014-09-30 11:19:51 +0100150
Soby Mathew8595b872015-01-06 15:36:38 +0000151 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100152 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100153 * enter the final wfi which will power down this CPU. This function
154 * might return if the power down was abandoned for any reason, e.g.
155 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100156 */
Soby Mathew981487a2015-07-13 14:10:57 +0100157 psci_cpu_suspend_start(&ep,
158 target_pwrlvl,
159 &state_info,
160 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100161
Soby Mathew74e52a72014-10-02 16:56:51 +0100162 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163}
164
Soby Mathew011ca182015-07-29 17:05:03 +0100165
166int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000167{
168 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100169 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000170 entry_point_info_t ep;
171
Soby Mathew96168382014-12-17 14:47:57 +0000172 /* Check if the current CPU is the last ON CPU in the system */
173 if (!psci_is_last_on_cpu())
174 return PSCI_E_DENIED;
175
Soby Mathewf1f97a12015-07-15 12:13:26 +0100176 /* Validate the entry point and get the entry_point_info */
177 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000178 if (rc != PSCI_E_SUCCESS)
179 return rc;
180
Soby Mathew981487a2015-07-13 14:10:57 +0100181 /* Query the psci_power_state for system suspend */
182 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000183
Soby Mathew981487a2015-07-13 14:10:57 +0100184 /* Ensure that the psci_power_state makes sense */
185 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
186 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
187 == PSCI_E_SUCCESS);
188 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000189
190 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100191 * Do what is needed to enter the system suspend state. This function
192 * might return if the power down was abandoned for any reason, e.g.
193 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000194 */
Soby Mathew981487a2015-07-13 14:10:57 +0100195 psci_cpu_suspend_start(&ep,
196 PLAT_MAX_PWR_LVL,
197 &state_info,
198 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000199
Soby Mathew96168382014-12-17 14:47:57 +0000200 return PSCI_E_SUCCESS;
201}
202
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203int psci_cpu_off(void)
204{
205 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100206 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100209 * Do what is needed to power off this CPU and possible higher power
210 * levels if it able to do so. Upon success, enter the final wfi
211 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212 */
Soby Mathew981487a2015-07-13 14:10:57 +0100213 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100214
Achin Gupta3140a9e2013-12-02 16:23:12 +0000215 /*
216 * The only error cpu_off can return is E_DENIED. So check if that's
217 * indeed the case.
218 */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100219 assert(rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
221 return rc;
222}
223
Soby Mathew011ca182015-07-29 17:05:03 +0100224int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225 unsigned int lowest_affinity_level)
226{
Soby Mathew981487a2015-07-13 14:10:57 +0100227 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100228
Soby Mathew981487a2015-07-13 14:10:57 +0100229 /* We dont support level higher than PSCI_CPU_PWR_LVL */
230 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
231 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
Soby Mathew981487a2015-07-13 14:10:57 +0100233 /* Calculate the cpu index of the target */
234 target_idx = plat_core_pos_by_mpidr(target_affinity);
235 if (target_idx == -1)
236 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000237
Soby Mathew981487a2015-07-13 14:10:57 +0100238 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239}
240
Soby Mathew011ca182015-07-29 17:05:03 +0100241int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242{
Soby Mathew110fe362014-10-23 10:35:34 +0100243 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100244 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100245
246 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
247 if (rc != PSCI_TOS_UP_MIG_CAP)
248 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
249 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
250
251 /*
252 * Migrate should only be invoked on the CPU where
253 * the Secure OS is resident.
254 */
255 if (resident_cpu_mpidr != read_mpidr_el1())
256 return PSCI_E_NOT_PRESENT;
257
258 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100259 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100260 if (rc != PSCI_E_SUCCESS)
261 return PSCI_E_INVALID_PARAMS;
262
263 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
264
265 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
266 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
267
268 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100269}
270
Soby Mathew110fe362014-10-23 10:35:34 +0100271int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272{
Soby Mathew011ca182015-07-29 17:05:03 +0100273 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100274
275 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276}
277
Soby Mathew110fe362014-10-23 10:35:34 +0100278long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279{
Soby Mathew011ca182015-07-29 17:05:03 +0100280 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100281 int rc;
282
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100284 * Return value of this depends upon what
285 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286 */
Soby Mathew110fe362014-10-23 10:35:34 +0100287 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
288 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
289 return PSCI_E_INVALID_PARAMS;
290
291 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292}
293
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000294int psci_features(unsigned int psci_fid)
295{
Soby Mathew011ca182015-07-29 17:05:03 +0100296 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000297
298 /* Check if it is a 64 bit function */
299 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
300 local_caps &= PSCI_CAP_64BIT_MASK;
301
302 /* Check for invalid fid */
303 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
304 && is_psci_fid(psci_fid)))
305 return PSCI_E_NOT_SUPPORTED;
306
307
308 /* Check if the psci fid is supported or not */
309 if (!(local_caps & define_psci_cap(psci_fid)))
310 return PSCI_E_NOT_SUPPORTED;
311
312 /* Format the feature flags */
313 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
314 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
315 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100316 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000317 */
Soby Mathew981487a2015-07-13 14:10:57 +0100318 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000319 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
320 }
321
322 /* Return 0 for all other fid's */
323 return PSCI_E_SUCCESS;
324}
325
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000326/*******************************************************************************
327 * PSCI top level handler for servicing SMCs.
328 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100329u_register_t psci_smc_handler(uint32_t smc_fid,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100330 u_register_t x1,
331 u_register_t x2,
332 u_register_t x3,
333 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000334 void *cookie,
335 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100336 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000337{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100338 if (is_caller_secure(flags))
Soby Mathewd0194872016-04-29 19:01:30 +0100339 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000340
Soby Mathew61e615b2015-01-15 11:49:49 +0000341 /* Check the fid against the capabilities */
342 if (!(psci_caps & define_psci_cap(smc_fid)))
Soby Mathewd0194872016-04-29 19:01:30 +0100343 return SMC_UNK;
Soby Mathew61e615b2015-01-15 11:49:49 +0000344
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100345 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
346 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000347
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100348 x1 = (uint32_t)x1;
349 x2 = (uint32_t)x2;
350 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000351
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100352 switch (smc_fid) {
353 case PSCI_VERSION:
Soby Mathewd0194872016-04-29 19:01:30 +0100354 return psci_version();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000355
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100356 case PSCI_CPU_OFF:
Soby Mathewd0194872016-04-29 19:01:30 +0100357 return psci_cpu_off();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000358
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100359 case PSCI_CPU_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100360 return psci_cpu_suspend(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000361
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100362 case PSCI_CPU_ON_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100363 return psci_cpu_on(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000364
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100365 case PSCI_AFFINITY_INFO_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100366 return psci_affinity_info(x1, x2);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000367
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100368 case PSCI_MIG_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100369 return psci_migrate(x1);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000370
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100371 case PSCI_MIG_INFO_TYPE:
Soby Mathewd0194872016-04-29 19:01:30 +0100372 return psci_migrate_info_type();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100373
374 case PSCI_MIG_INFO_UP_CPU_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100375 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100376
Soby Mathew96168382014-12-17 14:47:57 +0000377 case PSCI_SYSTEM_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100378 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000379
Juan Castillo4dc4a472014-08-12 11:17:06 +0100380 case PSCI_SYSTEM_OFF:
381 psci_system_off();
382 /* We should never return from psci_system_off() */
383
384 case PSCI_SYSTEM_RESET:
385 psci_system_reset();
386 /* We should never return from psci_system_reset() */
387
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000388 case PSCI_FEATURES:
Soby Mathewd0194872016-04-29 19:01:30 +0100389 return psci_features(x1);
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000390
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100391#if ENABLE_PSCI_STAT
392 case PSCI_STAT_RESIDENCY_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100393 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100394
395 case PSCI_STAT_COUNT_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100396 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100397#endif
398
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100399 default:
400 break;
401 }
402 } else {
403 /* 64-bit PSCI function */
404
405 switch (smc_fid) {
406 case PSCI_CPU_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100407 return psci_cpu_suspend(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100408
409 case PSCI_CPU_ON_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100410 return psci_cpu_on(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100411
412 case PSCI_AFFINITY_INFO_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100413 return psci_affinity_info(x1, x2);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100414
415 case PSCI_MIG_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100416 return psci_migrate(x1);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100417
418 case PSCI_MIG_INFO_UP_CPU_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100419 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100420
Soby Mathew96168382014-12-17 14:47:57 +0000421 case PSCI_SYSTEM_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100422 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000423
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100424#if ENABLE_PSCI_STAT
425 case PSCI_STAT_RESIDENCY_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100426 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100427
428 case PSCI_STAT_COUNT_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100429 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100430#endif
431
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100432 default:
433 break;
434 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000435 }
436
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100437 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
Soby Mathewd0194872016-04-29 19:01:30 +0100438 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000439}