Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Summer Qin | 13b95c2 | 2018-03-02 15:51:14 +0800 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 9 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 10 | /* Enable the dynamic translation tables library. */ |
| 11 | #ifdef AARCH32 |
| 12 | # if defined(IMAGE_BL32) && RESET_TO_SP_MIN |
| 13 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 14 | # endif |
| 15 | #else |
| 16 | # if defined(IMAGE_BL31) && RESET_TO_BL31 |
| 17 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 18 | # endif |
| 19 | #endif /* AARCH32 */ |
| 20 | |
| 21 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 22 | #include <arm_def.h> |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 23 | #include <board_css_def.h> |
| 24 | #include <common_def.h> |
| 25 | #include <css_def.h> |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 26 | #if TRUSTED_BOARD_BOOT |
| 27 | #include <mbedtls_config.h> |
| 28 | #endif |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 29 | #include <soc_css_def.h> |
| 30 | #include <tzc400.h> |
| 31 | #include <v2m_def.h> |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 32 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 33 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 34 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 35 | /* Juno supports system power domain */ |
| 36 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 37 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 38 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 39 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 40 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 41 | JUNO_CLUSTER1_CORE_COUNT) |
| 42 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 43 | /* Cryptocell HW Base address */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 44 | #define PLAT_CRYPTOCELL_BASE UL(0x60050000) |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 45 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 46 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 47 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 48 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 49 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 50 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 51 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 52 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 53 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 54 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 55 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 56 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 57 | /* Use the bypass address */ |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 58 | #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ |
| 59 | BL1_ROM_BYPASS_OFFSET) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 60 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 61 | #define NSRAM_BASE UL(0x2e000000) |
| 62 | #define NSRAM_SIZE UL(0x00008000) /* 32KB */ |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 63 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 64 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 65 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 66 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 67 | /* |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 68 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 69 | */ |
| 70 | |
| 71 | #if USE_ROMLIB |
| 72 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 73 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
| 74 | #else |
| 75 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 76 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
| 77 | #endif |
| 78 | |
| 79 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 80 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 81 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 82 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 83 | */ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 84 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 85 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 86 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 87 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 88 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 89 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 90 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 91 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 92 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 93 | * plat_arm_mmap array defined for each BL stage. |
| 94 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 95 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 96 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 97 | # define MAX_XLAT_TABLES 4 |
| 98 | #endif |
| 99 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 100 | #ifdef IMAGE_BL2 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 101 | #ifdef SPD_opteed |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 102 | # define PLAT_ARM_MMAP_ENTRIES 11 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 103 | # define MAX_XLAT_TABLES 5 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 104 | #else |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 105 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 106 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 107 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 108 | #endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 109 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 110 | #ifdef IMAGE_BL2U |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 111 | # define PLAT_ARM_MMAP_ENTRIES 5 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 112 | # define MAX_XLAT_TABLES 3 |
| 113 | #endif |
| 114 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 115 | #ifdef IMAGE_BL31 |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 116 | # define PLAT_ARM_MMAP_ENTRIES 7 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 117 | # define MAX_XLAT_TABLES 3 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 118 | #endif |
| 119 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 120 | #ifdef IMAGE_BL32 |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 121 | # define PLAT_ARM_MMAP_ENTRIES 6 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 122 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 123 | #endif |
| 124 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 125 | /* |
| 126 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 127 | * plus a little space for growth. |
| 128 | */ |
| 129 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 130 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 131 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 132 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 133 | #endif |
| 134 | |
| 135 | /* |
| 136 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 137 | * little space for growth. |
| 138 | */ |
| 139 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 140 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 141 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) |
Amit Daniel Kachhap | 4a8c7f9 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 142 | #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 143 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 144 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 145 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1C000) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 146 | #endif |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 147 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 148 | # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 149 | #endif |
| 150 | |
| 151 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 152 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 153 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 154 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. |
| 155 | * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 156 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 157 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 158 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 159 | #if JUNO_AARCH32_EL3_RUNTIME |
| 160 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 161 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 162 | * calculated using the current BL32 PROGBITS debug size plus the sizes of |
| 163 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. |
| 164 | * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 165 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 166 | #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 167 | #endif |
| 168 | |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 169 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 170 | * Size of cacheable stacks |
| 171 | */ |
| 172 | #if defined(IMAGE_BL1) |
| 173 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 174 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 175 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 176 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 177 | # endif |
| 178 | #elif defined(IMAGE_BL2) |
| 179 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 180 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 181 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 182 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 183 | # endif |
| 184 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 185 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 186 | #elif defined(IMAGE_BL31) |
| 187 | # if PLAT_XLAT_TABLES_DYNAMIC |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 188 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 189 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 190 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 191 | # endif |
| 192 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 193 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 194 | #endif |
| 195 | |
| 196 | /* |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 197 | * Since free SRAM space is scant, enable the ASSERTION message size |
| 198 | * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). |
| 199 | */ |
| 200 | #define PLAT_LOG_LEVEL_ASSERT 40 |
| 201 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 202 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 203 | #define PLAT_ARM_CCI_BASE UL(0x2c090000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 204 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 205 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 206 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 207 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 208 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 209 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 210 | /* TZC related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 211 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 212 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 213 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 214 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 215 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 216 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 217 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 218 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 219 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 220 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 221 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 222 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 223 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 224 | /* |
| 225 | * Required ARM CSS based platform porting definitions |
| 226 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 227 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 228 | /* GIC related constants (no GICR in GIC-400) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 229 | #define PLAT_ARM_GICD_BASE UL(0x2c010000) |
| 230 | #define PLAT_ARM_GICC_BASE UL(0x2c02f000) |
| 231 | #define PLAT_ARM_GICH_BASE UL(0x2c04f000) |
| 232 | #define PLAT_ARM_GICV_BASE UL(0x2c06f000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 233 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 234 | /* MHU related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 235 | #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 236 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 237 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 238 | * Base address of the first memory region used for communication between AP |
| 239 | * and SCP. Used by the BOM and SCPI protocols. |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 240 | */ |
| 241 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 242 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 243 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 244 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 245 | * communication with the SCP. The configuration data is expected to be a |
| 246 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 247 | * which CPU is the primary, according to the shift and mask definitions below. |
| 248 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 249 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 250 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 251 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 252 | #endif |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 253 | |
| 254 | /* |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 255 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 256 | * SCP_BL2 size plus a little space for growth. |
| 257 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 258 | #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 259 | |
| 260 | /* |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 261 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 262 | * SCP_BL2U size plus a little space for growth. |
| 263 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 264 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 265 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 266 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 267 | CSS_G1S_IRQ_PROPS(grp), \ |
| 268 | ARM_G1S_IRQ_PROPS(grp), \ |
| 269 | INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 270 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 271 | INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 272 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 273 | INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 274 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 275 | INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 276 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 277 | INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 278 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 279 | INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 280 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 281 | INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 282 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 283 | INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 284 | (grp), GIC_INTR_CFG_LEVEL) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 285 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 286 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 287 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 288 | /* |
| 289 | * Required ARM CSS SoC based platform porting definitions |
| 290 | */ |
| 291 | |
| 292 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 293 | #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 294 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 295 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 296 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 297 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 298 | #endif /* PLATFORM_DEF_H */ |