Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <lib/utils_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/v2m_def.h> |
| 13 | #include <plat/arm/common/arm_def.h> |
| 14 | #include <plat/arm/common/arm_spm_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <plat/common/common_def.h> |
| 16 | |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 19 | /* Required platform porting definitions */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ |
| 21 | U(FVP_MAX_CPUS_PER_CLUSTER) * \ |
| 22 | U(FVP_MAX_PE_PER_CPU)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 23 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 24 | #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ |
| 25 | PLATFORM_CORE_COUNT + U(1)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 26 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 27 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 28 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 29 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 30 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 31 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 32 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 33 | /* |
| 34 | * Required ARM standard platform porting definitions |
| 35 | */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 36 | #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 38 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 39 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 40 | #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) |
| 41 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 42 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 43 | #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) |
| 44 | #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 45 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 46 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 47 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 48 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 49 | /* No SCP in FVP */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 50 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 51 | |
Sami Mujawar | a43ae7c | 2019-05-09 13:35:02 +0100 | [diff] [blame] | 52 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 53 | #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 54 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 55 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 56 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 57 | */ |
Sandrine Bailleux | afa91db | 2019-01-31 15:01:32 +0100 | [diff] [blame] | 58 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 59 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 60 | /* |
| 61 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 62 | * plat_arm_mmap array defined for each BL stage. |
| 63 | */ |
| 64 | #if defined(IMAGE_BL31) |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 65 | # if SPM_MM |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 66 | # define PLAT_ARM_MMAP_ENTRIES 9 |
Antonio Nino Diaz | 840627f | 2018-11-27 08:36:02 +0000 | [diff] [blame] | 67 | # define MAX_XLAT_TABLES 9 |
| 68 | # define PLAT_SP_IMAGE_MMAP_REGIONS 30 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 69 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 70 | # else |
| 71 | # define PLAT_ARM_MMAP_ENTRIES 8 |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 72 | # if USE_DEBUGFS |
| 73 | # define MAX_XLAT_TABLES 6 |
| 74 | # else |
| 75 | # define MAX_XLAT_TABLES 5 |
| 76 | # endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 77 | # endif |
| 78 | #elif defined(IMAGE_BL32) |
| 79 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 80 | # define MAX_XLAT_TABLES 5 |
| 81 | #elif !USE_ROMLIB |
| 82 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 83 | # define MAX_XLAT_TABLES 5 |
| 84 | #else |
| 85 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 86 | # define MAX_XLAT_TABLES 6 |
| 87 | #endif |
| 88 | |
| 89 | /* |
| 90 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 91 | * plus a little space for growth. |
| 92 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 93 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 94 | |
| 95 | /* |
| 96 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 97 | */ |
| 98 | |
| 99 | #if USE_ROMLIB |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 100 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 101 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 102 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 103 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 104 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 105 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 106 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 107 | #endif |
| 108 | |
| 109 | /* |
| 110 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 111 | * little space for growth. |
| 112 | */ |
| 113 | #if TRUSTED_BOARD_BOOT |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 114 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 115 | #else |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 116 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 117 | #endif |
| 118 | |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 119 | #if RESET_TO_BL31 |
| 120 | /* Size of Trusted SRAM - the first 4KB of shared memory */ |
| 121 | #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 122 | ARM_SHARED_RAM_SIZE) |
| 123 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 124 | /* |
| 125 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 126 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 127 | * BL2 and BL1-RW |
| 128 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 129 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 130 | #endif /* RESET_TO_BL31 */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 131 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 132 | #ifndef __aarch64__ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 133 | /* |
| 134 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 135 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 136 | * BL2 and BL1-RW |
| 137 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 138 | # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 139 | #endif |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 140 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 141 | /* |
| 142 | * Size of cacheable stacks |
| 143 | */ |
| 144 | #if defined(IMAGE_BL1) |
| 145 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 146 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 147 | # else |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 148 | # define PLATFORM_STACK_SIZE UL(0x500) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 149 | # endif |
| 150 | #elif defined(IMAGE_BL2) |
| 151 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 152 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 153 | # else |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 154 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 155 | # endif |
| 156 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 157 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 158 | #elif defined(IMAGE_BL31) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 159 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 160 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 161 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 162 | #endif |
| 163 | |
| 164 | #define MAX_IO_DEVICES 3 |
| 165 | #define MAX_IO_HANDLES 4 |
| 166 | |
| 167 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
| 168 | #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE |
| 169 | #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 170 | |
| 171 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
| 172 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 173 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 174 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 175 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 176 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 177 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 178 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 179 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 180 | #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 181 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 182 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 183 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 184 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 185 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 186 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 187 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 188 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 189 | #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 190 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 191 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 192 | #define PLAT_FVP_CCI400_BASE UL(0x2c090000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 193 | #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 |
| 194 | #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 |
| 195 | |
| 196 | /* CCI-500/CCI-550 on Base platform */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 197 | #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 198 | #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 |
| 199 | #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 200 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 201 | /* CCN related constants. Only CCN 502 is currently supported */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 202 | #define PLAT_ARM_CCN_BASE UL(0x2e000000) |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 203 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 204 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 205 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 206 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 207 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 208 | /* Mailbox base address */ |
| 209 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 210 | |
| 211 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 212 | /* TrustZone controller related constants |
| 213 | * |
| 214 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 215 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 216 | * Filter 1 : not connected |
| 217 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 218 | * Filter 3 : not connected |
| 219 | * Programming unconnected filters will have no effect at the |
| 220 | * moment. These filter could, however, be connected in future. |
| 221 | * So care should be taken not to configure the unused filters. |
| 222 | * |
| 223 | * Allow only non-secure access to all DRAM to supported devices. |
| 224 | * Give access to the CPUs and Virtio. Some devices |
| 225 | * would normally use the default ID so allow that too. |
| 226 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 227 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 228 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 229 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 230 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 231 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 232 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 233 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 234 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 235 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 236 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 237 | /* |
| 238 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
| 239 | * FVP. They could be overriden at runtime in case the FVP implements the legacy |
| 240 | * VE memory map. |
| 241 | */ |
| 242 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 243 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 244 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 245 | |
| 246 | /* |
| 247 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 248 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 249 | * as Group 0 interrupts. |
| 250 | */ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 251 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 252 | ARM_G1S_IRQ_PROPS(grp), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 253 | INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 254 | GIC_INTR_CFG_LEVEL), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 255 | INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 256 | GIC_INTR_CFG_LEVEL) |
| 257 | |
| 258 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 259 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 260 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 261 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 262 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 263 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 264 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 265 | |
Sughosh Ganu | d284b57 | 2018-11-14 10:42:46 +0530 | [diff] [blame] | 266 | #define PLAT_SP_PRI PLAT_RAS_PRI |
| 267 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 268 | /* |
| 269 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 270 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 271 | #ifdef __aarch64__ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 272 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 273 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 274 | #else |
| 275 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 276 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 277 | #endif |
| 278 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 279 | #endif /* PLATFORM_DEF_H */ |