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git01.mediatek.com / filogic / atf / 02576935c3c830ef77786741f62d31b73dc53ebb / . / include / lib / cpus / aarch64 / cortex_x2.h
blob: 863b8c8d3787c47fa171adffbe26a772e8dd0b9f [file] [log] [blame]
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]1/*
Bipin Ravi2f73d972022-01-20 00:01:04 -0600[diff] [blame]2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_X2_H
8#define CORTEX_X2_H
9
10#define CORTEX_X2_MIDR U(0x410FD480)
11
Bipin Ravi86499742022-01-18 01:59:06 -0600[diff] [blame]12/* Cortex-X2 loop count for CVE-2022-23960 mitigation */
13#define CORTEX_X2_BHB_LOOP_COUNT U(32)
14
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
18#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
Bipin Ravi2f73d972022-01-20 00:01:04 -0600[diff] [blame]19#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]20
21/*******************************************************************************
johpow01f6c37de2021-12-03 11:27:33 -0600[diff] [blame]22 * CPU Extended Control register 2 specific definitions
23 ******************************************************************************/
24#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
25
26#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
27#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
28#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
29
30/*******************************************************************************
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]31 * CPU Power Control register specific definitions
32 ******************************************************************************/
33#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
34#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
35
johpow0115f10bd2021-12-01 17:40:39 -0600[diff] [blame]36/*******************************************************************************
Bipin Ravic6b65212022-03-08 10:37:43 -0600[diff] [blame]37 * CPU Auxiliary Control Register definitions
38 ******************************************************************************/
39#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0
40#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
41
42/*******************************************************************************
Bipin Ravi4e315c32022-07-12 17:13:01 -0500[diff] [blame]43 * CPU Auxiliary Control Register 2 definitions
44 ******************************************************************************/
45#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1
46#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
47
48/*******************************************************************************
johpow0115f10bd2021-12-01 17:40:39 -0600[diff] [blame]49 * CPU Auxiliary Control Register 5 definitions
50 ******************************************************************************/
51#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
Bipin Ravi78b72082022-02-06 01:29:31 -0600[diff] [blame]52#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
johpow0115f10bd2021-12-01 17:40:39 -0600[diff] [blame]53
Bipin Ravi9ad54782022-01-20 00:42:05 -0600[diff] [blame]54/*******************************************************************************
55 * CPU Implementation Specific Selected Instruction registers
56 ******************************************************************************/
57#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
58#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
59#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
60#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
61
johpow01a3810e82021-05-18 15:23:31 -0500[diff] [blame]62#endif /* CORTEX_X2_H */