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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +08002 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
Hadi Asyrafi67942302019-10-22 13:28:51 +080010#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080011#include <tools_share/uuid.h>
12
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080013#include "socfpga_fcs.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080014#include "socfpga_mailbox.h"
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080015#include "socfpga_reset_manager.h"
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080016#include "socfpga_sip_svc.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080017
Hadi Asyrafi616da772019-06-27 11:34:03 +080018
19/* Total buffer the driver can hold */
20#define FPGA_CONFIG_BUFFER_SIZE 4
21
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080022static int current_block, current_buffer;
23static int read_block, max_blocks, is_partial_reconfig;
24static uint32_t send_id, rcv_id;
25static uint32_t bytes_per_block, blocks_submitted;
Hadi Asyrafi616da772019-06-27 11:34:03 +080026
Hadi Asyrafi616da772019-06-27 11:34:03 +080027
28/* SiP Service UUID */
29DEFINE_SVC_UUID2(intl_svc_uid,
30 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
31 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
32
Hadi Asyraficee6aa92019-12-17 15:25:04 +080033static uint64_t socfpga_sip_handler(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +080034 uint64_t x1,
35 uint64_t x2,
36 uint64_t x3,
37 uint64_t x4,
38 void *cookie,
39 void *handle,
40 uint64_t flags)
41{
42 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
43 SMC_RET1(handle, SMC_UNK);
44}
45
46struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
47
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080048static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
Hadi Asyrafi616da772019-06-27 11:34:03 +080049{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +080050 uint32_t args[3];
Hadi Asyrafi616da772019-06-27 11:34:03 +080051
52 while (max_blocks > 0 && buffer->size > buffer->size_written) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080053 args[0] = (1<<8);
54 args[1] = buffer->addr + buffer->size_written;
55 if (buffer->size - buffer->size_written <= bytes_per_block) {
Hadi Asyrafi616da772019-06-27 11:34:03 +080056 args[2] = buffer->size - buffer->size_written;
Hadi Asyrafi616da772019-06-27 11:34:03 +080057 current_buffer++;
58 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080059 } else
Hadi Asyrafi616da772019-06-27 11:34:03 +080060 args[2] = bytes_per_block;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080061
62 buffer->size_written += args[2];
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080063 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +080064 3U, CMD_INDIRECT);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080065
66 buffer->subblocks_sent++;
Hadi Asyrafi616da772019-06-27 11:34:03 +080067 max_blocks--;
68 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080069
70 return !max_blocks;
Hadi Asyrafi616da772019-06-27 11:34:03 +080071}
72
73static int intel_fpga_sdm_write_all(void)
74{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080075 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
76 if (intel_fpga_sdm_write_buffer(
77 &fpga_config_buffers[current_buffer]))
78 break;
Hadi Asyrafi616da772019-06-27 11:34:03 +080079 return 0;
80}
81
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080082static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
Hadi Asyrafi616da772019-06-27 11:34:03 +080083{
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080084 uint32_t ret;
85
86 if (query_type == 1)
Sieu Mun Tang24682662022-02-19 21:49:48 +080087 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false);
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080088 else
Sieu Mun Tang24682662022-02-19 21:49:48 +080089 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080090
91 if (ret) {
92 if (ret == MBOX_CFGSTAT_STATE_CONFIG)
93 return INTEL_SIP_SMC_STATUS_BUSY;
94 else
95 return INTEL_SIP_SMC_STATUS_ERROR;
96 }
97
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080098 if (query_type != 1) {
99 /* full reconfiguration */
100 if (!is_partial_reconfig)
101 socfpga_bridges_enable(); /* Enable bridge */
102 }
103
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800104 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800105}
106
107static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
108{
109 int i;
110
111 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
112 if (fpga_config_buffers[i].block_number == current_block) {
113 fpga_config_buffers[i].subblocks_sent--;
114 if (fpga_config_buffers[i].subblocks_sent == 0
115 && fpga_config_buffers[i].size <=
116 fpga_config_buffers[i].size_written) {
117 fpga_config_buffers[i].write_requested = 0;
118 current_block++;
119 *buffer_addr_completed =
120 fpga_config_buffers[i].addr;
121 return 0;
122 }
123 }
124 }
125
126 return -1;
127}
128
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800129static int intel_fpga_config_completed_write(uint32_t *completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800130 uint32_t *count, uint32_t *job_id)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800131{
Hadi Asyrafi616da772019-06-27 11:34:03 +0800132 uint32_t resp[5];
Sieu Mun Tang24682662022-02-19 21:49:48 +0800133 unsigned int resp_len = ARRAY_SIZE(resp);
134 int status = INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800135 int all_completed = 1;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800136 *count = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800137
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800138 while (*count < 3) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800139
Sieu Mun Tang24682662022-02-19 21:49:48 +0800140 status = mailbox_read_response(job_id,
141 resp, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800142
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800143 if (status < 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800144 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800145 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800146
Hadi Asyrafi616da772019-06-27 11:34:03 +0800147 max_blocks++;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800148
Hadi Asyrafi616da772019-06-27 11:34:03 +0800149 if (mark_last_buffer_xfer_completed(
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800150 &completed_addr[*count]) == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800151 *count = *count + 1;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800152 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800153 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800154 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800155 }
156
157 if (*count <= 0) {
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800158 if (status != MBOX_NO_RESPONSE &&
159 status != MBOX_TIMEOUT && resp_len != 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800160 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800161 return INTEL_SIP_SMC_STATUS_ERROR;
162 }
163
164 *count = 0;
165 }
166
167 intel_fpga_sdm_write_all();
168
169 if (*count > 0)
170 status = INTEL_SIP_SMC_STATUS_OK;
171 else if (*count == 0)
172 status = INTEL_SIP_SMC_STATUS_BUSY;
173
174 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
175 if (fpga_config_buffers[i].write_requested != 0) {
176 all_completed = 0;
177 break;
178 }
179 }
180
181 if (all_completed == 1)
182 return INTEL_SIP_SMC_STATUS_OK;
183
184 return status;
185}
186
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800187static int intel_fpga_config_start(uint32_t config_type)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800188{
Sieu Mun Tang24682662022-02-19 21:49:48 +0800189 uint32_t argument = 0x1;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800190 uint32_t response[3];
191 int status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800192 unsigned int size = 0;
193 unsigned int resp_len = ARRAY_SIZE(response);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800194
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800195 is_partial_reconfig = config_type;
196
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800197 mailbox_clear_response();
198
Sieu Mun Tang24682662022-02-19 21:49:48 +0800199 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
200 CMD_CASUAL, NULL, NULL);
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800201
Sieu Mun Tang24682662022-02-19 21:49:48 +0800202 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
203 CMD_CASUAL, response, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800204
205 if (status < 0)
206 return status;
207
208 max_blocks = response[0];
209 bytes_per_block = response[1];
210
211 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
212 fpga_config_buffers[i].size = 0;
213 fpga_config_buffers[i].size_written = 0;
214 fpga_config_buffers[i].addr = 0;
215 fpga_config_buffers[i].write_requested = 0;
216 fpga_config_buffers[i].block_number = 0;
217 fpga_config_buffers[i].subblocks_sent = 0;
218 }
219
220 blocks_submitted = 0;
221 current_block = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800222 read_block = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800223 current_buffer = 0;
224
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800225 /* full reconfiguration */
226 if (!is_partial_reconfig) {
227 /* Disable bridge */
228 socfpga_bridges_disable();
229 }
230
Hadi Asyrafi616da772019-06-27 11:34:03 +0800231 return 0;
232}
233
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800234static bool is_fpga_config_buffer_full(void)
235{
236 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
237 if (!fpga_config_buffers[i].write_requested)
238 return false;
239 return true;
240}
241
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800242bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800243{
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +0800244 if (!addr && !size) {
245 return true;
246 }
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800247 if (size > (UINT64_MAX - addr))
248 return false;
Abdul Halim, Muhammad Hadi Asyrafie59b9992020-02-11 20:17:05 +0800249 if (addr < BL31_LIMIT)
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800250 return false;
251 if (addr + size > DRAM_BASE + DRAM_SIZE)
252 return false;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800253
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800254 return true;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800255}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800256
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800257static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800258{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800259 int i;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800260
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800261 intel_fpga_sdm_write_all();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800262
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800263 if (!is_address_in_ddr_range(mem, size) ||
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800264 is_fpga_config_buffer_full())
265 return INTEL_SIP_SMC_STATUS_REJECTED;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800266
267 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800268 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
269
270 if (!fpga_config_buffers[j].write_requested) {
271 fpga_config_buffers[j].addr = mem;
272 fpga_config_buffers[j].size = size;
273 fpga_config_buffers[j].size_written = 0;
274 fpga_config_buffers[j].write_requested = 1;
275 fpga_config_buffers[j].block_number =
Hadi Asyrafi616da772019-06-27 11:34:03 +0800276 blocks_submitted++;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800277 fpga_config_buffers[j].subblocks_sent = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800278 break;
279 }
280 }
281
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800282 if (is_fpga_config_buffer_full())
283 return INTEL_SIP_SMC_STATUS_BUSY;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800284
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800285 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800286}
287
Hadi Asyrafi67942302019-10-22 13:28:51 +0800288static int is_out_of_sec_range(uint64_t reg_addr)
289{
290 switch (reg_addr) {
291 case(0xF8011100): /* ECCCTRL1 */
292 case(0xF8011104): /* ECCCTRL2 */
293 case(0xF8011110): /* ERRINTEN */
294 case(0xF8011114): /* ERRINTENS */
295 case(0xF8011118): /* ERRINTENR */
296 case(0xF801111C): /* INTMODE */
297 case(0xF8011120): /* INTSTAT */
298 case(0xF8011124): /* DIAGINTTEST */
299 case(0xF801112C): /* DERRADDRA */
300 case(0xFFD12028): /* SDMMCGRP_CTRL */
301 case(0xFFD12044): /* EMAC0 */
302 case(0xFFD12048): /* EMAC1 */
303 case(0xFFD1204C): /* EMAC2 */
304 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
305 case(0xFFD12094): /* ECC_INT_MASK_SET */
306 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
307 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
308 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
309 case(0xFFD120C0): /* NOC_TIMEOUT */
310 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
311 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
312 case(0xFFD120D0): /* NOC_IDLEACK */
313 case(0xFFD120D4): /* NOC_IDLESTATUS */
314 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
315 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
316 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
317 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
318 return 0;
319
320 default:
321 break;
322 }
323
324 return -1;
325}
326
327/* Secure register access */
328uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
329{
330 if (is_out_of_sec_range(reg_addr))
331 return INTEL_SIP_SMC_STATUS_ERROR;
332
333 *retval = mmio_read_32(reg_addr);
334
335 return INTEL_SIP_SMC_STATUS_OK;
336}
337
338uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
339 uint32_t *retval)
340{
341 if (is_out_of_sec_range(reg_addr))
342 return INTEL_SIP_SMC_STATUS_ERROR;
343
344 mmio_write_32(reg_addr, val);
345
346 return intel_secure_reg_read(reg_addr, retval);
347}
348
349uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
350 uint32_t val, uint32_t *retval)
351{
352 if (!intel_secure_reg_read(reg_addr, retval)) {
353 *retval &= ~mask;
Siew Chin Lima0763152021-07-10 00:55:35 +0800354 *retval |= val & mask;
Hadi Asyrafi67942302019-10-22 13:28:51 +0800355 return intel_secure_reg_write(reg_addr, *retval, retval);
356 }
357
358 return INTEL_SIP_SMC_STATUS_ERROR;
359}
360
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800361/* Intel Remote System Update (RSU) services */
362uint64_t intel_rsu_update_address;
363
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800364static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800365{
366 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800367 return INTEL_SIP_SMC_RSU_ERROR;
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800368
369 return INTEL_SIP_SMC_STATUS_OK;
370}
371
372static uint32_t intel_rsu_update(uint64_t update_address)
373{
374 intel_rsu_update_address = update_address;
375 return INTEL_SIP_SMC_STATUS_OK;
376}
377
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800378static uint32_t intel_rsu_notify(uint32_t execution_stage)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800379{
Abdul Halim, Muhammad Hadi Asyrafie59b9992020-02-11 20:17:05 +0800380 if (mailbox_hps_stage_notify(execution_stage) < 0)
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800381 return INTEL_SIP_SMC_RSU_ERROR;
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800382
383 return INTEL_SIP_SMC_STATUS_OK;
384}
385
386static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
387 uint32_t *ret_stat)
388{
389 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800390 return INTEL_SIP_SMC_RSU_ERROR;
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800391
392 *ret_stat = respbuf[8];
393 return INTEL_SIP_SMC_STATUS_OK;
394}
395
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800396/* Mailbox services */
Sieu Mun Tang24682662022-02-19 21:49:48 +0800397static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
398 unsigned int len,
399 uint32_t urgent, uint32_t *response,
400 unsigned int resp_len, int *mbox_status,
401 unsigned int *len_in_resp)
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800402{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800403 *len_in_resp = 0;
404 *mbox_status = 0;
405
406 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len))
407 return INTEL_SIP_SMC_STATUS_REJECTED;
408
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800409 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
Sieu Mun Tang24682662022-02-19 21:49:48 +0800410 response, &resp_len);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800411
412 if (status < 0) {
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800413 *mbox_status = -status;
414 return INTEL_SIP_SMC_STATUS_ERROR;
415 }
416
417 *mbox_status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800418 *len_in_resp = resp_len;
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800419 return INTEL_SIP_SMC_STATUS_OK;
420}
421
Hadi Asyrafi616da772019-06-27 11:34:03 +0800422/*
423 * This function is responsible for handling all SiP calls from the NS world
424 */
425
426uintptr_t sip_smc_handler(uint32_t smc_fid,
427 u_register_t x1,
428 u_register_t x2,
429 u_register_t x3,
430 u_register_t x4,
431 void *cookie,
432 void *handle,
433 u_register_t flags)
434{
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800435 uint32_t retval = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800436 uint32_t completed_addr[3];
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800437 uint64_t rsu_respbuf[9];
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800438 int status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800439 int mbox_status;
440 unsigned int len_in_resp;
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800441 u_register_t x5, x6;
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +0800442
Hadi Asyrafi616da772019-06-27 11:34:03 +0800443 switch (smc_fid) {
444 case SIP_SVC_UID:
445 /* Return UID to the caller */
446 SMC_UUID_RET(handle, intl_svc_uid);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800447
Hadi Asyrafi616da772019-06-27 11:34:03 +0800448 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +0800449 status = intel_mailbox_fpga_config_isdone(x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800450 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800451
Hadi Asyrafi616da772019-06-27 11:34:03 +0800452 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
453 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
454 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
455 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
456 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800457
Hadi Asyrafi616da772019-06-27 11:34:03 +0800458 case INTEL_SIP_SMC_FPGA_CONFIG_START:
459 status = intel_fpga_config_start(x1);
460 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800461
Hadi Asyrafi616da772019-06-27 11:34:03 +0800462 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
463 status = intel_fpga_config_write(x1, x2);
464 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800465
Hadi Asyrafi616da772019-06-27 11:34:03 +0800466 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
467 status = intel_fpga_config_completed_write(completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800468 &retval, &rcv_id);
469 switch (retval) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800470 case 1:
471 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
472 completed_addr[0], 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800473
Hadi Asyrafi616da772019-06-27 11:34:03 +0800474 case 2:
475 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
476 completed_addr[0],
477 completed_addr[1], 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800478
Hadi Asyrafi616da772019-06-27 11:34:03 +0800479 case 3:
480 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
481 completed_addr[0],
482 completed_addr[1],
483 completed_addr[2]);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800484
Hadi Asyrafi616da772019-06-27 11:34:03 +0800485 case 0:
486 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800487
Hadi Asyrafi616da772019-06-27 11:34:03 +0800488 default:
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800489 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800490 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
491 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800492
493 case INTEL_SIP_SMC_REG_READ:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800494 status = intel_secure_reg_read(x1, &retval);
495 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800496
497 case INTEL_SIP_SMC_REG_WRITE:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800498 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
499 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800500
501 case INTEL_SIP_SMC_REG_UPDATE:
502 status = intel_secure_reg_update(x1, (uint32_t)x2,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800503 (uint32_t)x3, &retval);
504 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800505
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800506 case INTEL_SIP_SMC_RSU_STATUS:
507 status = intel_rsu_status(rsu_respbuf,
508 ARRAY_SIZE(rsu_respbuf));
509 if (status) {
510 SMC_RET1(handle, status);
511 } else {
512 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
513 rsu_respbuf[2], rsu_respbuf[3]);
514 }
515
516 case INTEL_SIP_SMC_RSU_UPDATE:
517 status = intel_rsu_update(x1);
518 SMC_RET1(handle, status);
519
520 case INTEL_SIP_SMC_RSU_NOTIFY:
521 status = intel_rsu_notify(x1);
522 SMC_RET1(handle, status);
523
524 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
525 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800526 ARRAY_SIZE(rsu_respbuf), &retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800527 if (status) {
528 SMC_RET1(handle, status);
529 } else {
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800530 SMC_RET2(handle, status, retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800531 }
532
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800533 case INTEL_SIP_SMC_ECC_DBE:
534 status = intel_ecc_dbe_notification(x1);
535 SMC_RET1(handle, status);
536
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800537 case INTEL_SIP_SMC_MBOX_SEND_CMD:
538 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
539 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800540 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800541 (uint32_t *)x5, x6, &mbox_status,
542 &len_in_resp);
Sieu Mun Tangf02f0cb2022-02-19 20:36:41 +0800543 SMC_RET3(handle, status, mbox_status, len_in_resp);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800544
Hadi Asyrafi616da772019-06-27 11:34:03 +0800545 default:
546 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
547 cookie, handle, flags);
548 }
549}
550
551DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800552 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800553 OEN_SIP_START,
554 OEN_SIP_END,
555 SMC_TYPE_FAST,
556 NULL,
557 sip_smc_handler
558);
559
560DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800561 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800562 OEN_SIP_START,
563 OEN_SIP_END,
564 SMC_TYPE_YIELD,
565 NULL,
566 sip_smc_handler
567);