autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3015-ethernet-update-ppe-from-netsys2-to-netsys3.patch

From aaac91720ca1fd7679896286eac2b014e7150fca Mon Sep 17 00:00:00 2001
From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Date: Mon, 18 Mar 2024 16:35:07 +0800
Subject: [PATCH 15/24] ethernet-update-ppe-from-netsys2-to-netsys3

---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c   |  8 +++-
 drivers/net/ethernet/mediatek/mtk_eth_soc.h   |  7 ++--
 drivers/net/ethernet/mediatek/mtk_ppe.c       | 35 ++++++++++++++---
 drivers/net/ethernet/mediatek/mtk_ppe.h       | 38 ++++++++++++++++---
 .../net/ethernet/mediatek/mtk_ppe_offload.c   |  6 ++-
 drivers/net/ethernet/mediatek/mtk_ppe_regs.h  |  7 ++++
 6 files changed, 82 insertions(+), 19 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 952bf51..f477ff3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2447,7 +2447,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
 			skb_checksum_none_assert(skb);
 		skb->protocol = eth_type_trans(skb, netdev);
 
-#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 		hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2;
 		reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5);
 		if (hash != MTK_RXD5_FOE_ENTRY_V2) {
@@ -5798,7 +5798,8 @@ static int mtk_probe(struct platform_device *pdev)
 
 		for (i = 0; i < eth->ppe_num; i++) {
 			eth->ppe[i] = mtk_ppe_init(eth,
-						   eth->base + MTK_ETH_PPE_BASE + i * 0x400,
+						   eth->base + MTK_ETH_PPE_BASE +
+						   (i == 2 ? 0xC00 : i * 0x400),
 						   2, eth->soc->hash_way, i,
 						   eth->soc->has_accounting);
 			if (!eth->ppe[i]) {
@@ -6065,6 +6066,9 @@ static const struct mtk_soc_data mt7988_data = {
 	.required_clks = MT7988_CLKS_BITMAP,
 	.required_pctl = false,
 	.has_sram = true,
+	.has_accounting = true,
+	.hash_way = 4,
+	.offload_version = 2,
 	.rss_num = 4,
 	.txrx = {
 		.txd_size = sizeof(struct mtk_tx_dma_v2),
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 58547af..9c46ac1 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -137,9 +137,10 @@
 #define MTK_GDMA_UCS_EN		BIT(20)
 #define MTK_GDMA_STRP_CRC	BIT(16)
 #define MTK_GDMA_TO_PDMA	0x0
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 #define MTK_GDMA_TO_PPE0	0x3333
 #define MTK_GDMA_TO_PPE1	0x4444
+#define MTK_GDMA_TO_PPE2	0xcccc
 #else
 #define MTK_GDMA_TO_PPE0	0x4444
 #endif
@@ -2018,14 +2019,14 @@ extern u32 dbg_show_level;
 
 static inline void mtk_set_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe, u32 val)
 {
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	foe->ib1 |= FIELD_PREP(MTK_FOE_IB1_UNBIND_SRC_PORT, val);
 #endif
 }
 
 static inline u32 mtk_get_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe)
 {
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	return FIELD_GET(MTK_FOE_IB1_UNBIND_SRC_PORT, foe->ib1);
 #else
 	return 0;
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
index 8388f65..184e29d 100755
--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
@@ -91,7 +91,7 @@ static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe)
 
 int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
 {
-	u32 val, cnt_r0, cnt_r1, cnt_r2;
+	u32 val, cnt_r0, cnt_r1, cnt_r2, cnt_r3;
 	u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
 
 	val = FIELD_PREP(MTK_PPE_MIB_SER_CR_ADDR, index) | MTK_PPE_MIB_SER_CR_ST;
@@ -104,12 +104,23 @@ int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
 	cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
 	cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
 
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+	cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3);
+
+	byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
+	byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH_V2, cnt_r1);
+	pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_LOW_V2, cnt_r2);
+	pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R3_PKT_CNT_HIGH, cnt_r3);
+	*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
+	*packets = ((u64)pkt_cnt_high << 32) | pkt_cnt_low;
+#else
 	byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
 	byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
 	pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
 	pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
 	*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
 	*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
+#endif
 
 	return 0;
 }
@@ -211,7 +222,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
 	      MTK_FOE_IB1_BIND_CACHE;
 	entry->ib1 = val;
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) |
 #else
 	val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
@@ -403,7 +414,7 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
 
 	*ib2 &= ~MTK_FOE_IB2_PORT_MG;
 	*ib2 |= MTK_FOE_IB2_WDMA_WINFO;
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq);
 
 	l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
@@ -422,11 +433,16 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
 
 int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid)
 {
+	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
 	u32 *ib2 = mtk_foe_entry_ib2(entry);
 
 	*ib2 &= ~MTK_FOE_IB2_QID;
 	*ib2 |= FIELD_PREP(MTK_FOE_IB2_QID, qid);
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+	l2->tport_id = 1;
+#else
 	*ib2 |= MTK_FOE_IB2_PSE_QOS;
+#endif
 
 	return 0;
 }
@@ -922,13 +938,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
 	mtk_ppe_init_foe_table(ppe);
 	ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
 
-	val = MTK_PPE_TB_CFG_ENTRY_80B |
+	val =
+#if !defined(CONFIG_MEDIATEK_NETSYS_V3)
+	      MTK_PPE_TB_CFG_ENTRY_80B |
+#endif
 	      MTK_PPE_TB_CFG_AGE_NON_L4 |
 	      MTK_PPE_TB_CFG_AGE_UNBIND |
 	      MTK_PPE_TB_CFG_AGE_TCP |
 	      MTK_PPE_TB_CFG_AGE_UDP |
 	      MTK_PPE_TB_CFG_AGE_TCP_FIN |
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	      MTK_PPE_TB_CFG_INFO_SEL |
 #endif
 	      FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
@@ -988,12 +1007,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
 	      MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
 	      MTK_PPE_GLO_CFG_IP4_CS_DROP |
 	      MTK_PPE_GLO_CFG_MCAST_TB_EN |
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+	      MTK_PPE_GLO_CFG_CS0_PIPE_EN |
+	      MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN |
+#endif
 	      MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
 	ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
 
 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
 	ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
 #endif
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
index 5ab864f..5529d64 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
@@ -8,7 +8,10 @@
 #include <linux/bitfield.h>
 #include <linux/rhashtable.h>
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+#define MTK_MAX_PPE_NUM			3
+#define MTK_ETH_PPE_BASE		0x2000
+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
 #define MTK_MAX_PPE_NUM			2
 #define MTK_ETH_PPE_BASE		0x2000
 #else
@@ -22,7 +25,7 @@
 #define MTK_PPE_WAIT_TIMEOUT_US		1000000
 
 #define MTK_FOE_IB1_UNBIND_TIMESTAMP	GENMASK(7, 0)
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 #define MTK_FOE_IB1_UNBIND_SRC_PORT	GENMASK(11, 8)
 #define MTK_FOE_IB1_UNBIND_PACKETS	GENMASK(19, 12)
 #define MTK_FOE_IB1_UNBIND_PREBIND	BIT(22)
@@ -70,7 +73,7 @@ enum {
 	MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
 };
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 #define MTK_FOE_IB2_QID			GENMASK(6, 0)
 #define MTK_FOE_IB2_PORT_MG		BIT(7)
 #define MTK_FOE_IB2_PSE_QOS		BIT(8)
@@ -98,7 +101,18 @@ enum {
 
 #define MTK_FOE_IB2_DSCP		GENMASK(31, 24)
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+#define MTK_FOE_WINFO_WCID		GENMASK(15, 0)
+#define MTK_FOE_WINFO_BSS		GENMASK(23, 16)
+
+#define MTK_FOE_WINFO_PAO_USR_INFO	GENMASK(15, 0)
+#define MTK_FOE_WINFO_PAO_TID		GENMASK(19, 16)
+#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE	BIT(20)
+#define MTK_FOE_WINFO_PAO_IS_PRIOR	BIT(21)
+#define MTK_FOE_WINFO_PAO_IS_SP		BIT(22)
+#define MTK_FOE_WINFO_PAO_HF		BIT(23)
+#define MTK_FOE_WINFO_PAO_AMSDU_EN	BIT(24)
+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
 #define MTK_FOE_WINFO_BSS		GENMASK(5, 0)
 #define MTK_FOE_WINFO_WCID		GENMASK(15, 6)
 #else
@@ -128,7 +142,17 @@ struct mtk_foe_mac_info {
 	u16 pppoe_id;
 	u16 src_mac_lo;
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+	u16 minfo;
+	u16 resv1;
+	u32 winfo;
+	u32 winfo_pao;
+	u16 cdrt_id:8;
+	u16 tops_entry:6;
+	u16 resv3:2;
+	u16 tport_id:4;
+	u16 resv4:12;
+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
 	u16 minfo;
 	u16 winfo;
 #endif
@@ -249,7 +273,9 @@ struct mtk_foe_entry {
 		struct mtk_foe_ipv4_dslite dslite;
 		struct mtk_foe_ipv6 ipv6;
 		struct mtk_foe_ipv6_6rd ipv6_6rd;
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+		u32 data[31];
+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
 		u32 data[23];
 #else
 		u32 data[19];
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
index 3bc50a4..f0c63da 100755
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
@@ -195,7 +195,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
 		mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,
 				       info.wcid);
 		pse_port = PSE_PPE0_PORT;
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 		if (info.wdma_idx == 0)
 			pse_port = PSE_WDMA0_PORT;
 		else if (info.wdma_idx == 1)
@@ -218,6 +218,8 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
 		pse_port = PSE_GDM1_PORT;
 	else if (dev == eth->netdev[1])
 		pse_port = PSE_GDM2_PORT;
+	else if (dev == eth->netdev[2])
+		pse_port = PSE_GDM3_PORT;
 	else
 		return -EOPNOTSUPP;
 
@@ -376,7 +378,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
 	if (err)
 		return err;
 
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
 	if (idev && idev->netdev_ops->ndo_fill_receive_path) {
 		ctx.dev = idev;
 		idev->netdev_ops->ndo_fill_receive_path(&ctx, &path);
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
index 8d3ebe1..55b9b0c 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
@@ -18,6 +18,8 @@
 #define MTK_PPE_GLO_CFG_UDP_LITE_EN		BIT(10)
 #define MTK_PPE_GLO_CFG_UDP_LEN_DROP		BIT(11)
 #define MTK_PPE_GLO_CFG_MCAST_ENTRIES		GNEMASK(13, 12)
+#define MTK_PPE_GLO_CFG_CS0_PIPE_EN		BIT(29)
+#define MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN	BIT(30)
 #define MTK_PPE_GLO_CFG_BUSY			BIT(31)
 
 #define MTK_PPE_FLOW_CFG			0x204
@@ -155,9 +157,14 @@ enum {
 #define MTK_PPE_MIB_SER_R1			0x344
 #define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW		GENMASK(31, 16)
 #define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH	GENMASK(15, 0)
+#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH_V2	GENMASK(31, 0)
 
 #define MTK_PPE_MIB_SER_R2			0x348
 #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH		GENMASK(23, 0)
+#define MTK_PPE_MIB_SER_R2_PKT_CNT_LOW_V2	GENMASK(31, 0)
+
+#define MTK_PPE_MIB_SER_R3			0x34C
+#define MTK_PPE_MIB_SER_R3_PKT_CNT_HIGH		GENMASK(31, 0)
 
 #define MTK_PPE_MIB_CACHE_CTL			0x350
 #define MTK_PPE_MIB_CACHE_CTL_EN		BIT(0)
-- 
2.18.0