blob: 872a2793a3391993169bb47beeab7d78b2c13ef2 [file] [log] [blame]
developer64b431b2023-08-26 01:04:45 +08001From 06c3b8d434290affb720808a38315a78e94c9923 Mon Sep 17 00:00:00 2001
developer0aaf79d2023-08-21 14:10:16 +08002From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
developer64b431b2023-08-26 01:04:45 +08003Date: Sat, 26 Aug 2023 00:45:40 +0800
developer0aaf79d2023-08-21 14:10:16 +08004Subject: [PATCH] 999-3017-ethernet-update-ppe-from-mt7986-to-mt7988
5
6---
7 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++---
developer64b431b2023-08-26 01:04:45 +08008 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 9 +++--
developer0aaf79d2023-08-21 14:10:16 +08009 drivers/net/ethernet/mediatek/mtk_ppe.c | 18 ++++++---
developer64b431b2023-08-26 01:04:45 +080010 drivers/net/ethernet/mediatek/mtk_ppe.h | 38 ++++++++++++++++---
developer0aaf79d2023-08-21 14:10:16 +080011 .../net/ethernet/mediatek/mtk_ppe_offload.c | 6 ++-
developer64b431b2023-08-26 01:04:45 +080012 5 files changed, 64 insertions(+), 21 deletions(-)
developer0aaf79d2023-08-21 14:10:16 +080013
developeree39bcf2023-06-16 08:03:30 +080014diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer64b431b2023-08-26 01:04:45 +080015index a370547..239c25d 100644
developeree39bcf2023-06-16 08:03:30 +080016--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
17+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer64b431b2023-08-26 01:04:45 +080018@@ -2272,17 +2272,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
developeree39bcf2023-06-16 08:03:30 +080019 skb_checksum_none_assert(skb);
20 skb->protocol = eth_type_trans(skb, netdev);
21
22-#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
23- hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2;
24+#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
25+ hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2;
26 #else
27- hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
28+ hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
29 #endif
30 if (hash != MTK_RXD4_FOE_ENTRY) {
31 hash = jhash_1word(hash, 0);
32 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
33 }
34
35-#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
36+#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
37 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5);
38 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) {
39 for (i = 0; i < eth->ppe_num; i++) {
developer64b431b2023-08-26 01:04:45 +080040@@ -5071,7 +5071,8 @@ static int mtk_probe(struct platform_device *pdev)
developeree39bcf2023-06-16 08:03:30 +080041
42 for (i = 0; i < eth->ppe_num; i++) {
43 eth->ppe[i] = mtk_ppe_init(eth,
44- eth->base + MTK_ETH_PPE_BASE + i * 0x400,
45+ eth->base + MTK_ETH_PPE_BASE +
46+ (i == 2 ? 0xC00 : i * 0x400),
47 2, eth->soc->hash_way, i,
48 eth->soc->has_accounting);
49 if (!eth->ppe[i]) {
developer64b431b2023-08-26 01:04:45 +080050@@ -5338,6 +5339,9 @@ static const struct mtk_soc_data mt7988_data = {
developeree39bcf2023-06-16 08:03:30 +080051 .required_clks = MT7988_CLKS_BITMAP,
52 .required_pctl = false,
53 .has_sram = true,
54+ .has_accounting = true,
55+ .hash_way = 4,
56+ .offload_version = 2,
developer0aaf79d2023-08-21 14:10:16 +080057 .rss_num = 4,
developeree39bcf2023-06-16 08:03:30 +080058 .txrx = {
59 .txd_size = sizeof(struct mtk_tx_dma_v2),
developeree39bcf2023-06-16 08:03:30 +080060diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
developer64b431b2023-08-26 01:04:45 +080061index a7892e2..cd19c8d 100644
developeree39bcf2023-06-16 08:03:30 +080062--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
63+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
developer0aaf79d2023-08-21 14:10:16 +080064@@ -130,9 +130,10 @@
developeree39bcf2023-06-16 08:03:30 +080065 #define MTK_GDMA_UCS_EN BIT(20)
66 #define MTK_GDMA_STRP_CRC BIT(16)
67 #define MTK_GDMA_TO_PDMA 0x0
68-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
69+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
70 #define MTK_GDMA_TO_PPE0 0x3333
71 #define MTK_GDMA_TO_PPE1 0x4444
72+#define MTK_GMAC_TO_PPE2 0xcccc
73 #else
developer0aaf79d2023-08-21 14:10:16 +080074 #define MTK_GDMA_TO_PPE0 0x4444
75 #endif
developer64b431b2023-08-26 01:04:45 +080076@@ -1939,13 +1940,15 @@ extern u32 dbg_show_level;
77
78 static inline void mtk_set_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe, u32 val)
79 {
80- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
81+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
82+ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
83 foe->ib1 |= FIELD_PREP(MTK_FOE_IB1_UNBIND_SRC_PORT, val);
84 }
85
86 static inline u32 mtk_get_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe)
87 {
88- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
89+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
90+ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
91 return FIELD_GET(MTK_FOE_IB1_UNBIND_SRC_PORT, foe->ib1);
92
93 return 0;
developeree39bcf2023-06-16 08:03:30 +080094diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
developer64b431b2023-08-26 01:04:45 +080095index 0d4ae28..308d5a1 100755
developeree39bcf2023-06-16 08:03:30 +080096--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
97+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
98@@ -211,7 +211,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
99 MTK_FOE_IB1_BIND_CACHE;
100 entry->ib1 = val;
101
102-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
103+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
104 val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) |
105 #else
106 val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
107@@ -403,7 +403,7 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
108
109 *ib2 &= ~MTK_FOE_IB2_PORT_MG;
110 *ib2 |= MTK_FOE_IB2_WDMA_WINFO;
111-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
112+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
113 *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq);
114
115 l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
116@@ -422,11 +422,16 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
117
118 int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid)
119 {
120+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
121 u32 *ib2 = mtk_foe_entry_ib2(entry);
122
123 *ib2 &= ~MTK_FOE_IB2_QID;
124 *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID, qid);
125+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
126+ l2->tport_id = 1;
127+#else
128 *ib2 |= MTK_FOE_IB2_PSE_QOS;
129+#endif
130
131 return 0;
132 }
developer64b431b2023-08-26 01:04:45 +0800133@@ -922,13 +927,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
developeree39bcf2023-06-16 08:03:30 +0800134 mtk_ppe_init_foe_table(ppe);
135 ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
136
137- val = MTK_PPE_TB_CFG_ENTRY_80B |
138+ val =
139+#if !defined(CONFIG_MEDIATEK_NETSYS_V3)
140+ MTK_PPE_TB_CFG_ENTRY_80B |
141+#endif
142 MTK_PPE_TB_CFG_AGE_NON_L4 |
143 MTK_PPE_TB_CFG_AGE_UNBIND |
144 MTK_PPE_TB_CFG_AGE_TCP |
145 MTK_PPE_TB_CFG_AGE_UDP |
146 MTK_PPE_TB_CFG_AGE_TCP_FIN |
147-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
148+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
149 MTK_PPE_TB_CFG_INFO_SEL |
150 #endif
151 FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
developer64b431b2023-08-26 01:04:45 +0800152@@ -992,7 +1000,7 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
developeree39bcf2023-06-16 08:03:30 +0800153
154 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
155
156-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
157+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
158 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
159 ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
160 #endif
161diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
developer64b431b2023-08-26 01:04:45 +0800162index 5ab864f..5529d64 100644
developeree39bcf2023-06-16 08:03:30 +0800163--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
164+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
165@@ -8,7 +8,10 @@
166 #include <linux/bitfield.h>
167 #include <linux/rhashtable.h>
168
169-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
170+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
171+#define MTK_MAX_PPE_NUM 3
172+#define MTK_ETH_PPE_BASE 0x2000
173+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
174 #define MTK_MAX_PPE_NUM 2
175 #define MTK_ETH_PPE_BASE 0x2000
176 #else
developer0aaf79d2023-08-21 14:10:16 +0800177@@ -22,7 +25,7 @@
developeree39bcf2023-06-16 08:03:30 +0800178 #define MTK_PPE_WAIT_TIMEOUT_US 1000000
179
180 #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
181-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
182+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
183 #define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8)
184 #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12)
185 #define MTK_FOE_IB1_UNBIND_PREBIND BIT(22)
developer0aaf79d2023-08-21 14:10:16 +0800186@@ -70,7 +73,7 @@ enum {
developeree39bcf2023-06-16 08:03:30 +0800187 MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
188 };
189
190-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
191+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
192 #define MTK_FOE_IB2_QID GENMASK(6, 0)
193 #define MTK_FOE_IB2_PORT_MG BIT(7)
194 #define MTK_FOE_IB2_PSE_QOS BIT(8)
developer0aaf79d2023-08-21 14:10:16 +0800195@@ -98,7 +101,18 @@ enum {
developeree39bcf2023-06-16 08:03:30 +0800196
197 #define MTK_FOE_IB2_DSCP GENMASK(31, 24)
198
199-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
200+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
201+#define MTK_FOE_WINFO_WCID GENMASK(15, 0)
202+#define MTK_FOE_WINFO_BSS GENMASK(23, 16)
203+
204+#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0)
205+#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16)
206+#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20)
207+#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21)
208+#define MTK_FOE_WINFO_PAO_IS_SP BIT(22)
209+#define MTK_FOE_WINFO_PAO_HF BIT(23)
210+#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24)
211+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
212 #define MTK_FOE_WINFO_BSS GENMASK(5, 0)
213 #define MTK_FOE_WINFO_WCID GENMASK(15, 6)
214 #else
developer0aaf79d2023-08-21 14:10:16 +0800215@@ -128,7 +142,17 @@ struct mtk_foe_mac_info {
developeree39bcf2023-06-16 08:03:30 +0800216 u16 pppoe_id;
217 u16 src_mac_lo;
218
219-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
220+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
221+ u16 minfo;
222+ u16 resv1;
223+ u32 winfo;
224+ u32 winfo_pao;
225+ u16 cdrt_id:8;
226+ u16 tops_entry:6;
227+ u16 resv3:2;
228+ u16 tport_id:4;
229+ u16 resv4:12;
230+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
231 u16 minfo;
232 u16 winfo;
233 #endif
developer0aaf79d2023-08-21 14:10:16 +0800234@@ -249,7 +273,9 @@ struct mtk_foe_entry {
developeree39bcf2023-06-16 08:03:30 +0800235 struct mtk_foe_ipv4_dslite dslite;
236 struct mtk_foe_ipv6 ipv6;
237 struct mtk_foe_ipv6_6rd ipv6_6rd;
238-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
239+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
240+ u32 data[31];
241+#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
242 u32 data[23];
243 #else
244 u32 data[19];
245diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
developer64b431b2023-08-26 01:04:45 +0800246index 3bc50a4..f0c63da 100755
developeree39bcf2023-06-16 08:03:30 +0800247--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
248+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
249@@ -195,7 +195,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
250 mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,
251 info.wcid);
252 pse_port = PSE_PPE0_PORT;
253-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
254+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
255 if (info.wdma_idx == 0)
256 pse_port = PSE_WDMA0_PORT;
257 else if (info.wdma_idx == 1)
developer0aaf79d2023-08-21 14:10:16 +0800258@@ -218,6 +218,8 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
developeree39bcf2023-06-16 08:03:30 +0800259 pse_port = PSE_GDM1_PORT;
260 else if (dev == eth->netdev[1])
261 pse_port = PSE_GDM2_PORT;
262+ else if (dev == eth->netdev[2])
263+ pse_port = PSE_GDM3_PORT;
264 else
265 return -EOPNOTSUPP;
266
developer0aaf79d2023-08-21 14:10:16 +0800267@@ -376,7 +378,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
268 if (err)
269 return err;
developeree39bcf2023-06-16 08:03:30 +0800270
developeree39bcf2023-06-16 08:03:30 +0800271-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
272+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
273 if (idev && idev->netdev_ops->ndo_fill_receive_path) {
274 ctx.dev = idev;
275 idev->netdev_ops->ndo_fill_receive_path(&ctx, &path);
developer0aaf79d2023-08-21 14:10:16 +0800276--
2772.18.0
278