developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 1 | From 5481f7ecbd3cfffd8234bc8e952a6e07f42de76c Mon Sep 17 00:00:00 2001 |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 2 | From: Bo-Cun Chen <bc-bocun.chen@mediatek.com> |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 3 | Date: Tue, 21 Nov 2023 16:42:01 +0800 |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 4 | Subject: [PATCH 16/22] ethernet-update-ppe-from-netsys2-to-netsys3 |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
| 7 | drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++--- |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 8 | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 ++-- |
| 9 | drivers/net/ethernet/mediatek/mtk_ppe.c | 35 ++++++++++++++--- |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 10 | drivers/net/ethernet/mediatek/mtk_ppe.h | 38 ++++++++++++++++--- |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 11 | .../net/ethernet/mediatek/mtk_ppe_offload.c | 6 ++- |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 12 | drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 7 ++++ |
| 13 | 6 files changed, 85 insertions(+), 22 deletions(-) |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 14 | |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 15 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 16 | index 850bc4f..8910d40 100644 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 17 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 18 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 19 | @@ -2248,17 +2248,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 20 | skb_checksum_none_assert(skb); |
| 21 | skb->protocol = eth_type_trans(skb, netdev); |
| 22 | |
| 23 | -#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) |
| 24 | - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 25 | +#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 26 | + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 27 | #else |
| 28 | - hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 29 | + hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 30 | #endif |
| 31 | if (hash != MTK_RXD4_FOE_ENTRY) { |
| 32 | hash = jhash_1word(hash, 0); |
| 33 | skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); |
| 34 | } |
| 35 | |
| 36 | -#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) |
| 37 | +#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 38 | reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5); |
| 39 | if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) { |
| 40 | for (i = 0; i < eth->ppe_num; i++) { |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 41 | @@ -5290,7 +5290,8 @@ static int mtk_probe(struct platform_device *pdev) |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 42 | |
| 43 | for (i = 0; i < eth->ppe_num; i++) { |
| 44 | eth->ppe[i] = mtk_ppe_init(eth, |
| 45 | - eth->base + MTK_ETH_PPE_BASE + i * 0x400, |
| 46 | + eth->base + MTK_ETH_PPE_BASE + |
| 47 | + (i == 2 ? 0xC00 : i * 0x400), |
| 48 | 2, eth->soc->hash_way, i, |
| 49 | eth->soc->has_accounting); |
| 50 | if (!eth->ppe[i]) { |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 51 | @@ -5557,6 +5558,9 @@ static const struct mtk_soc_data mt7988_data = { |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 52 | .required_clks = MT7988_CLKS_BITMAP, |
| 53 | .required_pctl = false, |
| 54 | .has_sram = true, |
| 55 | + .has_accounting = true, |
| 56 | + .hash_way = 4, |
| 57 | + .offload_version = 2, |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 58 | .rss_num = 4, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 59 | .txrx = { |
| 60 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 61 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 62 | index 9c77f14..c7d36c5 100644 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 63 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 64 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 65 | @@ -134,9 +134,10 @@ |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 66 | #define MTK_GDMA_UCS_EN BIT(20) |
| 67 | #define MTK_GDMA_STRP_CRC BIT(16) |
| 68 | #define MTK_GDMA_TO_PDMA 0x0 |
| 69 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 70 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 71 | #define MTK_GDMA_TO_PPE0 0x3333 |
| 72 | #define MTK_GDMA_TO_PPE1 0x4444 |
developer | 47b4f91 | 2023-11-16 11:44:30 +0800 | [diff] [blame] | 73 | +#define MTK_GDMA_TO_PPE2 0xcccc |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 74 | #else |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 75 | #define MTK_GDMA_TO_PPE0 0x4444 |
| 76 | #endif |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 77 | @@ -1978,14 +1979,14 @@ extern u32 dbg_show_level; |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 78 | |
| 79 | static inline void mtk_set_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe, u32 val) |
| 80 | { |
developer | c1d06e1 | 2023-10-26 21:52:08 +0800 | [diff] [blame] | 81 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 82 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 83 | foe->ib1 |= FIELD_PREP(MTK_FOE_IB1_UNBIND_SRC_PORT, val); |
| 84 | #endif |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static inline u32 mtk_get_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe) |
| 88 | { |
developer | c1d06e1 | 2023-10-26 21:52:08 +0800 | [diff] [blame] | 89 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 90 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 91 | return FIELD_GET(MTK_FOE_IB1_UNBIND_SRC_PORT, foe->ib1); |
| 92 | #else |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 93 | return 0; |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 94 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 95 | index 8388f65..184e29d 100755 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 96 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 97 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 98 | @@ -91,7 +91,7 @@ static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe) |
| 99 | |
| 100 | int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets) |
| 101 | { |
| 102 | - u32 val, cnt_r0, cnt_r1, cnt_r2; |
| 103 | + u32 val, cnt_r0, cnt_r1, cnt_r2, cnt_r3; |
| 104 | u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high; |
| 105 | |
| 106 | val = FIELD_PREP(MTK_PPE_MIB_SER_CR_ADDR, index) | MTK_PPE_MIB_SER_CR_ST; |
| 107 | @@ -104,12 +104,23 @@ int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets) |
| 108 | cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); |
| 109 | cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2); |
| 110 | |
| 111 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 112 | + cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); |
| 113 | + |
| 114 | + byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); |
| 115 | + byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH_V2, cnt_r1); |
| 116 | + pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_LOW_V2, cnt_r2); |
| 117 | + pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R3_PKT_CNT_HIGH, cnt_r3); |
| 118 | + *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; |
| 119 | + *packets = ((u64)pkt_cnt_high << 32) | pkt_cnt_low; |
| 120 | +#else |
| 121 | byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); |
| 122 | byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); |
| 123 | pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); |
| 124 | pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); |
| 125 | *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; |
| 126 | *packets = (pkt_cnt_high << 16) | pkt_cnt_low; |
| 127 | +#endif |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | @@ -211,7 +222,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 132 | MTK_FOE_IB1_BIND_CACHE; |
| 133 | entry->ib1 = val; |
| 134 | |
| 135 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 136 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 137 | val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) | |
| 138 | #else |
| 139 | val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 140 | @@ -403,7 +414,7 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 141 | |
| 142 | *ib2 &= ~MTK_FOE_IB2_PORT_MG; |
| 143 | *ib2 |= MTK_FOE_IB2_WDMA_WINFO; |
| 144 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 145 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 146 | *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq); |
| 147 | |
| 148 | l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 149 | @@ -422,11 +433,16 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 150 | |
| 151 | int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid) |
| 152 | { |
| 153 | + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); |
| 154 | u32 *ib2 = mtk_foe_entry_ib2(entry); |
| 155 | |
| 156 | *ib2 &= ~MTK_FOE_IB2_QID; |
| 157 | *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID, qid); |
| 158 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 159 | + l2->tport_id = 1; |
| 160 | +#else |
| 161 | *ib2 |= MTK_FOE_IB2_PSE_QOS; |
| 162 | +#endif |
| 163 | |
| 164 | return 0; |
| 165 | } |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 166 | @@ -922,13 +938,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 167 | mtk_ppe_init_foe_table(ppe); |
| 168 | ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); |
| 169 | |
| 170 | - val = MTK_PPE_TB_CFG_ENTRY_80B | |
| 171 | + val = |
| 172 | +#if !defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 173 | + MTK_PPE_TB_CFG_ENTRY_80B | |
| 174 | +#endif |
| 175 | MTK_PPE_TB_CFG_AGE_NON_L4 | |
| 176 | MTK_PPE_TB_CFG_AGE_UNBIND | |
| 177 | MTK_PPE_TB_CFG_AGE_TCP | |
| 178 | MTK_PPE_TB_CFG_AGE_UDP | |
| 179 | MTK_PPE_TB_CFG_AGE_TCP_FIN | |
| 180 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 181 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 182 | MTK_PPE_TB_CFG_INFO_SEL | |
| 183 | #endif |
| 184 | FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 185 | @@ -988,12 +1007,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 186 | MTK_PPE_GLO_CFG_IP4_L4_CS_DROP | |
| 187 | MTK_PPE_GLO_CFG_IP4_CS_DROP | |
| 188 | MTK_PPE_GLO_CFG_MCAST_TB_EN | |
| 189 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 190 | + MTK_PPE_GLO_CFG_CS0_PIPE_EN | |
| 191 | + MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN | |
| 192 | +#endif |
| 193 | MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE; |
| 194 | ppe_w32(ppe, MTK_PPE_GLO_CFG, val); |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 195 | |
| 196 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); |
| 197 | |
| 198 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 199 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 200 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); |
| 201 | ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); |
| 202 | #endif |
| 203 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 204 | index 5ab864f..5529d64 100644 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 205 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 206 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 207 | @@ -8,7 +8,10 @@ |
| 208 | #include <linux/bitfield.h> |
| 209 | #include <linux/rhashtable.h> |
| 210 | |
| 211 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 212 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 213 | +#define MTK_MAX_PPE_NUM 3 |
| 214 | +#define MTK_ETH_PPE_BASE 0x2000 |
| 215 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 216 | #define MTK_MAX_PPE_NUM 2 |
| 217 | #define MTK_ETH_PPE_BASE 0x2000 |
| 218 | #else |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 219 | @@ -22,7 +25,7 @@ |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 220 | #define MTK_PPE_WAIT_TIMEOUT_US 1000000 |
| 221 | |
| 222 | #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) |
| 223 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 224 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 225 | #define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8) |
| 226 | #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12) |
| 227 | #define MTK_FOE_IB1_UNBIND_PREBIND BIT(22) |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 228 | @@ -70,7 +73,7 @@ enum { |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 229 | MTK_PPE_PKT_TYPE_IPV6_6RD = 7, |
| 230 | }; |
| 231 | |
| 232 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 233 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 234 | #define MTK_FOE_IB2_QID GENMASK(6, 0) |
| 235 | #define MTK_FOE_IB2_PORT_MG BIT(7) |
| 236 | #define MTK_FOE_IB2_PSE_QOS BIT(8) |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 237 | @@ -98,7 +101,18 @@ enum { |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 238 | |
| 239 | #define MTK_FOE_IB2_DSCP GENMASK(31, 24) |
| 240 | |
| 241 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 242 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 243 | +#define MTK_FOE_WINFO_WCID GENMASK(15, 0) |
| 244 | +#define MTK_FOE_WINFO_BSS GENMASK(23, 16) |
| 245 | + |
| 246 | +#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0) |
| 247 | +#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16) |
| 248 | +#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20) |
| 249 | +#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21) |
| 250 | +#define MTK_FOE_WINFO_PAO_IS_SP BIT(22) |
| 251 | +#define MTK_FOE_WINFO_PAO_HF BIT(23) |
| 252 | +#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24) |
| 253 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 254 | #define MTK_FOE_WINFO_BSS GENMASK(5, 0) |
| 255 | #define MTK_FOE_WINFO_WCID GENMASK(15, 6) |
| 256 | #else |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 257 | @@ -128,7 +142,17 @@ struct mtk_foe_mac_info { |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 258 | u16 pppoe_id; |
| 259 | u16 src_mac_lo; |
| 260 | |
| 261 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 262 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 263 | + u16 minfo; |
| 264 | + u16 resv1; |
| 265 | + u32 winfo; |
| 266 | + u32 winfo_pao; |
| 267 | + u16 cdrt_id:8; |
| 268 | + u16 tops_entry:6; |
| 269 | + u16 resv3:2; |
| 270 | + u16 tport_id:4; |
| 271 | + u16 resv4:12; |
| 272 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 273 | u16 minfo; |
| 274 | u16 winfo; |
| 275 | #endif |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 276 | @@ -249,7 +273,9 @@ struct mtk_foe_entry { |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 277 | struct mtk_foe_ipv4_dslite dslite; |
| 278 | struct mtk_foe_ipv6 ipv6; |
| 279 | struct mtk_foe_ipv6_6rd ipv6_6rd; |
| 280 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 281 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 282 | + u32 data[31]; |
| 283 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 284 | u32 data[23]; |
| 285 | #else |
| 286 | u32 data[19]; |
| 287 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
developer | 64b431b | 2023-08-26 01:04:45 +0800 | [diff] [blame] | 288 | index 3bc50a4..f0c63da 100755 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 289 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 290 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 291 | @@ -195,7 +195,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 292 | mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss, |
| 293 | info.wcid); |
| 294 | pse_port = PSE_PPE0_PORT; |
| 295 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 296 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 297 | if (info.wdma_idx == 0) |
| 298 | pse_port = PSE_WDMA0_PORT; |
| 299 | else if (info.wdma_idx == 1) |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 300 | @@ -218,6 +218,8 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 301 | pse_port = PSE_GDM1_PORT; |
| 302 | else if (dev == eth->netdev[1]) |
| 303 | pse_port = PSE_GDM2_PORT; |
| 304 | + else if (dev == eth->netdev[2]) |
| 305 | + pse_port = PSE_GDM3_PORT; |
| 306 | else |
| 307 | return -EOPNOTSUPP; |
| 308 | |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 309 | @@ -376,7 +378,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f) |
| 310 | if (err) |
| 311 | return err; |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 312 | |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 313 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 314 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 315 | if (idev && idev->netdev_ops->ndo_fill_receive_path) { |
| 316 | ctx.dev = idev; |
| 317 | idev->netdev_ops->ndo_fill_receive_path(&ctx, &path); |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 318 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 319 | index 8d3ebe1..55b9b0c 100644 |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 320 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
| 321 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
developer | 6c97864 | 2023-11-21 17:59:56 +0800 | [diff] [blame^] | 322 | @@ -18,6 +18,8 @@ |
| 323 | #define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10) |
| 324 | #define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11) |
| 325 | #define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12) |
| 326 | +#define MTK_PPE_GLO_CFG_CS0_PIPE_EN BIT(29) |
| 327 | +#define MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN BIT(30) |
| 328 | #define MTK_PPE_GLO_CFG_BUSY BIT(31) |
| 329 | |
| 330 | #define MTK_PPE_FLOW_CFG 0x204 |
| 331 | @@ -155,9 +157,14 @@ enum { |
developer | 7f08cd0 | 2023-10-25 12:11:22 +0800 | [diff] [blame] | 332 | #define MTK_PPE_MIB_SER_R1 0x344 |
| 333 | #define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16) |
| 334 | #define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0) |
| 335 | +#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH_V2 GENMASK(31, 0) |
| 336 | |
| 337 | #define MTK_PPE_MIB_SER_R2 0x348 |
| 338 | #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) |
| 339 | +#define MTK_PPE_MIB_SER_R2_PKT_CNT_LOW_V2 GENMASK(31, 0) |
| 340 | + |
| 341 | +#define MTK_PPE_MIB_SER_R3 0x34C |
| 342 | +#define MTK_PPE_MIB_SER_R3_PKT_CNT_HIGH GENMASK(31, 0) |
| 343 | |
| 344 | #define MTK_PPE_MIB_CACHE_CTL 0x350 |
| 345 | #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) |
developer | 0aaf79d | 2023-08-21 14:10:16 +0800 | [diff] [blame] | 346 | -- |
| 347 | 2.18.0 |
| 348 | |