| developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TOPS_HWSPIN_LOCK_H_ |
| 9 | #define _TOPS_HWSPIN_LOCK_H_ |
| 10 | |
| 11 | #include <linux/types.h> |
| 12 | |
| 13 | #include "mbox.h" |
| 14 | |
| 15 | #define HWSPINLOCK_SLOT_MAX 16 |
| 16 | |
| 17 | #define HWSPINLOCK_TOP_BASE 0x10100 |
| 18 | #define HWSPINLOCK_CLUST_BASE 0x880000 |
| 19 | |
| 20 | enum hwspinlock_group { |
| 21 | HWSPINLOCK_GROUP_TOP, |
| 22 | HWSPINLOCK_GROUP_CLUST, |
| 23 | |
| 24 | __HWSPINLOCK_GROUP_MAX, |
| 25 | }; |
| 26 | |
| 27 | enum hwspinlock_top_slot { |
| 28 | HWSPINLOCK_TOP_SLOT_HPDMA_LOCK, |
| 29 | HWSPINLOCK_TOP_SLOT_HPDMA_PCH0, |
| 30 | HWSPINLOCK_TOP_SLOT_HPDMA_PCH1, |
| 31 | HWSPINLOCK_TOP_SLOT_HPDMA_PCH2, |
| 32 | HWSPINLOCK_TOP_SLOT_HPDMA_PCH3, |
| 33 | HWSPINLOCK_TOP_SLOT_5, |
| 34 | HWSPINLOCK_TOP_SLOT_6, |
| 35 | HWSPINLOCK_TOP_SLOT_7, |
| 36 | HWSPINLOCK_TOP_SLOT_8, |
| 37 | HWSPINLOCK_TOP_SLOT_9, |
| 38 | HWSPINLOCK_TOP_SLOT_10, |
| 39 | HWSPINLOCK_TOP_SLOT_11, |
| 40 | HWSPINLOCK_TOP_SLOT_12, |
| 41 | HWSPINLOCK_TOP_SLOT_13, |
| 42 | HWSPINLOCK_TOP_SLOT_14, |
| 43 | HWSPINLOCK_TOP_SLOT_15, |
| 44 | |
| 45 | __HWSPINLOCK_TOP_MAX = HWSPINLOCK_SLOT_MAX, |
| 46 | }; |
| 47 | |
| 48 | enum hwspinlock_clust_slot { |
| 49 | HWSPINLOCK_CLUST_SLOT_PRINTF, |
| 50 | HWSPINLOCK_CLUST_SLOT_HPDMA_LOCK, |
| 51 | HWSPINLOCK_CLUST_SLOT_HPDMA_PCH0, |
| 52 | HWSPINLOCK_CLUST_SLOT_HPDMA_PCH1, |
| 53 | HWSPINLOCK_CLUST_SLOT_HPDMA_PCH2, |
| 54 | HWSPINLOCK_CLUST_SLOT_HPDMA_PCH3, |
| 55 | HWSPINLOCK_CLUST_SLOT_6, |
| 56 | HWSPINLOCK_CLUST_SLOT_7, |
| 57 | HWSPINLOCK_CLUST_SLOT_8, |
| 58 | HWSPINLOCK_CLUST_SLOT_9, |
| 59 | HWSPINLOCK_CLUST_SLOT_10, |
| 60 | HWSPINLOCK_CLUST_SLOT_11, |
| 61 | HWSPINLOCK_CLUST_SLOT_12, |
| 62 | HWSPINLOCK_CLUST_SLOT_13, |
| 63 | HWSPINLOCK_CLUST_SLOT_14, |
| 64 | HWSPINLOCK_CLUST_SLOT_15, |
| 65 | |
| 66 | __HWSPINLOCK_CLUST_MAX = HWSPINLOCK_SLOT_MAX, |
| 67 | }; |
| 68 | |
| 69 | int mtk_tops_hwspin_try_lock(enum hwspinlock_group grp, u32 slot); |
| 70 | void mtk_tops_hwspin_lock(enum hwspinlock_group grp, u32 slot); |
| 71 | void mtk_tops_hwspin_unlock(enum hwspinlock_group grp, u32 slot); |
| 72 | int mtk_tops_hwspinlock_init(struct platform_device *pdev); |
| 73 | #endif /* _TOPS_HWSPIN_LOCK_H_ */ |