[][openwrt][mt7988][tops][TOPS Alpha release]
[Description]
Add alpha version of TOPS(tunnel offload processor system) and tops-tool
package.
TOPS package supports tunnel protocol HW offload. The support offload
tunnel protocols for Alpha version are L2oGRE and L2TPv2.
Notice that, TOPS only guarantees that inner packets are TCP. It is still
unstable for UDP inner packet flow.
tops-tool package provides several debug features such as logger, coredump
for TOPS.
[Release-log]
N/A
Change-Id: Iab6e4a89bebbe42c967f28e0c9e9c0611673f354
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7852683
diff --git a/package-21.02/kernel/tops/src/inc/hwspinlock.h b/package-21.02/kernel/tops/src/inc/hwspinlock.h
new file mode 100644
index 0000000..ee9e343
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/hwspinlock.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_HWSPIN_LOCK_H_
+#define _TOPS_HWSPIN_LOCK_H_
+
+#include <linux/types.h>
+
+#include "mbox.h"
+
+#define HWSPINLOCK_SLOT_MAX 16
+
+#define HWSPINLOCK_TOP_BASE 0x10100
+#define HWSPINLOCK_CLUST_BASE 0x880000
+
+enum hwspinlock_group {
+ HWSPINLOCK_GROUP_TOP,
+ HWSPINLOCK_GROUP_CLUST,
+
+ __HWSPINLOCK_GROUP_MAX,
+};
+
+enum hwspinlock_top_slot {
+ HWSPINLOCK_TOP_SLOT_HPDMA_LOCK,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH0,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH1,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH2,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH3,
+ HWSPINLOCK_TOP_SLOT_5,
+ HWSPINLOCK_TOP_SLOT_6,
+ HWSPINLOCK_TOP_SLOT_7,
+ HWSPINLOCK_TOP_SLOT_8,
+ HWSPINLOCK_TOP_SLOT_9,
+ HWSPINLOCK_TOP_SLOT_10,
+ HWSPINLOCK_TOP_SLOT_11,
+ HWSPINLOCK_TOP_SLOT_12,
+ HWSPINLOCK_TOP_SLOT_13,
+ HWSPINLOCK_TOP_SLOT_14,
+ HWSPINLOCK_TOP_SLOT_15,
+
+ __HWSPINLOCK_TOP_MAX = HWSPINLOCK_SLOT_MAX,
+};
+
+enum hwspinlock_clust_slot {
+ HWSPINLOCK_CLUST_SLOT_PRINTF,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_LOCK,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH0,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH1,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH2,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH3,
+ HWSPINLOCK_CLUST_SLOT_6,
+ HWSPINLOCK_CLUST_SLOT_7,
+ HWSPINLOCK_CLUST_SLOT_8,
+ HWSPINLOCK_CLUST_SLOT_9,
+ HWSPINLOCK_CLUST_SLOT_10,
+ HWSPINLOCK_CLUST_SLOT_11,
+ HWSPINLOCK_CLUST_SLOT_12,
+ HWSPINLOCK_CLUST_SLOT_13,
+ HWSPINLOCK_CLUST_SLOT_14,
+ HWSPINLOCK_CLUST_SLOT_15,
+
+ __HWSPINLOCK_CLUST_MAX = HWSPINLOCK_SLOT_MAX,
+};
+
+int mtk_tops_hwspin_try_lock(enum hwspinlock_group grp, u32 slot);
+void mtk_tops_hwspin_lock(enum hwspinlock_group grp, u32 slot);
+void mtk_tops_hwspin_unlock(enum hwspinlock_group grp, u32 slot);
+int mtk_tops_hwspinlock_init(struct platform_device *pdev);
+#endif /* _TOPS_HWSPIN_LOCK_H_ */