[][openwrt][mt7988][tops][TOPS Alpha release]
[Description]
Add alpha version of TOPS(tunnel offload processor system) and tops-tool
package.
TOPS package supports tunnel protocol HW offload. The support offload
tunnel protocols for Alpha version are L2oGRE and L2TPv2.
Notice that, TOPS only guarantees that inner packets are TCP. It is still
unstable for UDP inner packet flow.
tops-tool package provides several debug features such as logger, coredump
for TOPS.
[Release-log]
N/A
Change-Id: Iab6e4a89bebbe42c967f28e0c9e9c0611673f354
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7852683
diff --git a/package-21.02/kernel/tops/src/inc/ctrl.h b/package-21.02/kernel/tops/src/inc/ctrl.h
new file mode 100644
index 0000000..fb74e40
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/ctrl.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_CTRL_H_
+#define _TOPS_CTRL_H_
+
+#include <linux/platform_device.h>
+
+int mtk_tops_ctrl_init(struct platform_device *pdev);
+void mtk_tops_ctrl_deinit(struct platform_device *pdev);
+#endif /* _TOPS_CTRL_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/firmware.h b/package-21.02/kernel/tops/src/inc/firmware.h
new file mode 100644
index 0000000..663ea95
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/firmware.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_FW_H_
+#define _TOPS_FW_H_
+
+#include <linux/platform_device.h>
+#include <linux/time.h>
+
+enum tops_role_type {
+ TOPS_ROLE_TYPE_MGMT,
+ TOPS_ROLE_TYPE_CLUSTER,
+
+ __TOPS_ROLE_TYPE_MAX,
+};
+
+u64 mtk_tops_fw_get_git_commit_id(enum tops_role_type rtype);
+void mtk_tops_fw_get_built_date(enum tops_role_type rtype, struct tm *tm);
+u32 mtk_tops_fw_attr_get_num(enum tops_role_type rtype);
+const char *mtk_tops_fw_attr_get_property(enum tops_role_type rtype, u32 idx);
+const char *mtk_tops_fw_attr_get_value(enum tops_role_type rtype,
+ const char *property);
+
+int mtk_tops_fw_bring_up_default_cores(void);
+int mtk_tops_fw_bring_up_core(const char *fw_path);
+void mtk_tops_fw_clean_up(void);
+int mtk_tops_fw_init(struct platform_device *pdev);
+#endif /* _TOPS_FW_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/hpdma.h b/package-21.02/kernel/tops/src/inc/hpdma.h
new file mode 100644
index 0000000..4f3d08c
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/hpdma.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_HPDMA_H_
+#define _TOPS_HPDMA_H_
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+/* AXI DMA */
+#define TOPS_HPDMA_X_SRC(x) (0x100 * (x) + 0x0000)
+#define TOPS_HPDMA_X_DST(x) (0x100 * (x) + 0x0004)
+#define TOPS_HPDMA_X_NUM(x) (0x100 * (x) + 0x0008)
+#define TOPS_HPDMA_X_CTRL(x) (0x100 * (x) + 0x000C)
+#define TOPS_HPDMA_X_CLRIRQ(x) (0x100 * (x) + 0x0010)
+#define TOPS_HPDMA_X_START(x) (0x100 * (x) + 0x0014)
+#define TOPS_HPDMA_X_RRESP(x) (0x100 * (x) + 0x0018)
+#define TOPS_HPDMA_X_BRESP(x) (0x100 * (x) + 0x001C)
+#define TOPS_HPDMA_X_HW(x) (0x100 * (x) + 0x0020)
+#define TOPS_HPDMA_X_ERR(x) (0x100 * (x) + 0x0024)
+
+
+/* AXI DMA NUM */
+#define HPDMA_TOTALNUM_SHIFT (0)
+#define HPDMA_TOTALNUM_MASK GENMASK(15, 0)
+
+/* AXI DMA CTRL */
+#define HPDMA_AXLEN_SHIFT (0)
+#define HPDMA_AXLEN_MASK GENMASK(3, 0)
+#define HPDMA_AXSIZE_SHIFT (8)
+#define HPDMA_AXSIZE_MASK GENMASK(10, 8)
+#define HPDMA_IRQEN BIT(16)
+#define HPDMA_AWMODE_EN BIT(24)
+#define HPDMA_OUTSTD_SHIFT (25)
+#define HPDMA_OUTSTD_MASK GENMASK(29, 25)
+
+/* AXI DMA START */
+#define HPDMA_STATUS_SHIFT (0)
+#define HPDMA_STATUS_MASK GENMASK(0, 0)
+#define HPDMA_SKIP_RACE_SHIFT (7)
+#define HPDMA_SKIP_RACE_MASK GENMASK(7, 7)
+#define HPDMA_START BIT(15)
+
+/* AXI DMA RRESP */
+#define HPDMA_LOG_SHIFT (0)
+#define HPDMA_LOG_MASK GENMASK(15, 0)
+#define HPDMA_RESP_SHIFT (16)
+#define HPDMA_RESP_MASK GENMASK(17, 16)
+
+/* AXI DMA HW */
+#define HPDMA_FIFO_DEPTH_SHIFT (0)
+#define HPDMA_FIFO_DEPTH_MASK GENMASK(7, 0)
+#define HPDMA_MAX_AXSIZE_SHIFT (8)
+#define HPDMA_MAX_AXSIZE_MASK GENMASK(15, 8)
+
+enum hpdma_err {
+ AWMODE_ERR = 0x1 << 0,
+ AXSIZE_ERR = 0x1 << 1,
+ ARADDR_ERR = 0x1 << 2,
+ AWADDR_ERR = 0x1 << 3,
+ RACE_ERR = 0x1 << 4,
+};
+
+enum top_hpdma_req {
+ TOP_HPDMA_TNL_SYNC_REQ,
+
+ __TOP_HPDMA_REQ,
+};
+
+enum clust_hpdma_req {
+ CLUST_HPDMA_DUMMY_REQ,
+
+ __CLUST_HPDMA_REQ,
+};
+
+int mtk_tops_hpdma_init(void);
+void mtk_tops_hpdma_exit(void);
+#endif /* _TOPS_HPDMA_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/hwspinlock.h b/package-21.02/kernel/tops/src/inc/hwspinlock.h
new file mode 100644
index 0000000..ee9e343
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/hwspinlock.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_HWSPIN_LOCK_H_
+#define _TOPS_HWSPIN_LOCK_H_
+
+#include <linux/types.h>
+
+#include "mbox.h"
+
+#define HWSPINLOCK_SLOT_MAX 16
+
+#define HWSPINLOCK_TOP_BASE 0x10100
+#define HWSPINLOCK_CLUST_BASE 0x880000
+
+enum hwspinlock_group {
+ HWSPINLOCK_GROUP_TOP,
+ HWSPINLOCK_GROUP_CLUST,
+
+ __HWSPINLOCK_GROUP_MAX,
+};
+
+enum hwspinlock_top_slot {
+ HWSPINLOCK_TOP_SLOT_HPDMA_LOCK,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH0,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH1,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH2,
+ HWSPINLOCK_TOP_SLOT_HPDMA_PCH3,
+ HWSPINLOCK_TOP_SLOT_5,
+ HWSPINLOCK_TOP_SLOT_6,
+ HWSPINLOCK_TOP_SLOT_7,
+ HWSPINLOCK_TOP_SLOT_8,
+ HWSPINLOCK_TOP_SLOT_9,
+ HWSPINLOCK_TOP_SLOT_10,
+ HWSPINLOCK_TOP_SLOT_11,
+ HWSPINLOCK_TOP_SLOT_12,
+ HWSPINLOCK_TOP_SLOT_13,
+ HWSPINLOCK_TOP_SLOT_14,
+ HWSPINLOCK_TOP_SLOT_15,
+
+ __HWSPINLOCK_TOP_MAX = HWSPINLOCK_SLOT_MAX,
+};
+
+enum hwspinlock_clust_slot {
+ HWSPINLOCK_CLUST_SLOT_PRINTF,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_LOCK,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH0,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH1,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH2,
+ HWSPINLOCK_CLUST_SLOT_HPDMA_PCH3,
+ HWSPINLOCK_CLUST_SLOT_6,
+ HWSPINLOCK_CLUST_SLOT_7,
+ HWSPINLOCK_CLUST_SLOT_8,
+ HWSPINLOCK_CLUST_SLOT_9,
+ HWSPINLOCK_CLUST_SLOT_10,
+ HWSPINLOCK_CLUST_SLOT_11,
+ HWSPINLOCK_CLUST_SLOT_12,
+ HWSPINLOCK_CLUST_SLOT_13,
+ HWSPINLOCK_CLUST_SLOT_14,
+ HWSPINLOCK_CLUST_SLOT_15,
+
+ __HWSPINLOCK_CLUST_MAX = HWSPINLOCK_SLOT_MAX,
+};
+
+int mtk_tops_hwspin_try_lock(enum hwspinlock_group grp, u32 slot);
+void mtk_tops_hwspin_lock(enum hwspinlock_group grp, u32 slot);
+void mtk_tops_hwspin_unlock(enum hwspinlock_group grp, u32 slot);
+int mtk_tops_hwspinlock_init(struct platform_device *pdev);
+#endif /* _TOPS_HWSPIN_LOCK_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/internal.h b/package-21.02/kernel/tops/src/inc/internal.h
new file mode 100644
index 0000000..81e1ca1
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/internal.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_INTERNAL_H_
+#define _TOPS_INTERNAL_H_
+
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/io.h>
+
+extern struct device *tops_dev;
+
+#define TOPS_DBG(fmt, ...) dev_dbg(tops_dev, fmt, ##__VA_ARGS__)
+#define TOPS_INFO(fmt, ...) dev_info(tops_dev, fmt, ##__VA_ARGS__)
+#define TOPS_NOTICE(fmt, ...) dev_notice(tops_dev, fmt, ##__VA_ARGS__)
+#define TOPS_WARN(fmt, ...) dev_warn(tops_dev, fmt, ##__VA_ARGS__)
+#define TOPS_ERR(fmt, ...) dev_err(tops_dev, fmt, ##__VA_ARGS__)
+
+/* tops 32 bits read/write */
+#define setbits(addr, set) writel(readl(addr) | (set), (addr))
+#define clrbits(addr, clr) writel(readl(addr) & ~(clr), (addr))
+#define clrsetbits(addr, clr, set) writel((readl(addr) & ~(clr)) | (set), (addr))
+#endif /* _TOPS_INTERNAL_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/mbox.h b/package-21.02/kernel/tops/src/inc/mbox.h
new file mode 100644
index 0000000..002f2c6
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/mbox.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_MBOX_H_
+#define _TOPS_MBOX_H_
+
+#include <linux/list.h>
+
+#include "mbox_id.h"
+#include "tops.h"
+
+/* mbox device macros */
+#define MBOX_DEV(core_id, cmd) \
+ .core = core_id, \
+ .cmd_id = cmd,
+
+#define MBOX_SEND_DEV(core_id, cmd) \
+ { \
+ MBOX_DEV(core_id, cmd) \
+ }
+
+#define MBOX_SEND_MGMT_DEV(cmd) \
+ MBOX_SEND_DEV(CORE_MGMT, MBOX_AP2CM_CMD_ ## cmd)
+
+#define MBOX_SEND_OFFLOAD_DEV(core_id, cmd) \
+ MBOX_SEND_DEV(CORE_OFFLOAD_ ## core_id, MBOX_AP2CX_CMD_ ## cmd)
+
+#define MBOX_RECV_DEV(core_id, cmd, handler) \
+ { \
+ MBOX_DEV(core_id, cmd) \
+ .mbox_handler = handler, \
+ }
+
+#define MBOX_RECV_MGMT_DEV(cmd, handler) \
+ MBOX_RECV_DEV(CORE_MGMT, MBOX_CM2AP_CMD_ ## cmd, handler)
+
+#define MBOX_RECV_OFFLOAD_DEV(core_id, cmd, handler) \
+ MBOX_RECV_DEV(CORE_OFFLOAD_ ## core_id, MBOX_CX2AP_CMD_ ## cmd, handler)
+
+/* Base Address */
+#define MBOX_TOP_BASE (0x010000)
+#define MBOX_CLUST0_BASE (0x510000)
+
+/* TOP Mailbox */
+#define TOPS_TOP_CM_SLOT (MBOX_TOP_BASE + 0x000)
+#define TOPS_TOP_AP_SLOT (MBOX_TOP_BASE + 0x004)
+
+#define TOPS_TOP_AP_TO_CM_CMD_SET (MBOX_TOP_BASE + 0x200)
+#define TOPS_TOP_AP_TO_CM_CMD_CLR (MBOX_TOP_BASE + 0x204)
+#define TOPS_TOP_CM_TO_AP_CMD_SET (MBOX_TOP_BASE + 0x21C)
+#define TOPS_TOP_CM_TO_AP_CMD_CLR (MBOX_TOP_BASE + 0x220)
+
+#define TOPS_TOP_AP_TO_CM_MSG_N(n) (MBOX_TOP_BASE + 0x208 + 0x4 * (n))
+#define TOPS_TOP_CM_TO_AP_MSG_N(n) (MBOX_TOP_BASE + 0x224 + 0x4 * (n))
+
+/* CLUST Mailbox */
+#define TOPS_CLUST0_CX_SLOT(x) (MBOX_CLUST0_BASE + (0x4 * (x)))
+#define TOPS_CLUST0_CM_SLOT (MBOX_CLUST0_BASE + 0x10)
+#define TOPS_CLUST0_AP_SLOT (MBOX_CLUST0_BASE + 0x14)
+
+#define TOPS_CLUST0_CX_TO_CY_CMD_SET(x, y) \
+ (MBOX_CLUST0_BASE + 0x100 + ((x) * 0x200) + ((y) * 0x40))
+#define TOPS_CLUST0_CX_TO_CY_CMD_CLR(x, y) \
+ (MBOX_CLUST0_BASE + 0x104 + ((x) * 0x200) + ((y) * 0x40))
+#define TOPS_CLUST0_CX_TO_CM_CMD_SET(x) \
+ (MBOX_CLUST0_BASE + 0x200 + ((x) * 0x200))
+#define TOPS_CLUST0_CX_TO_CM_CMD_CLR(x) \
+ (MBOX_CLUST0_BASE + 0x204 + ((x) * 0x200))
+#define TOPS_CLUST0_CX_TO_AP_CMD_SET(x) \
+ (MBOX_CLUST0_BASE + 0x240 + ((x) * 0x200))
+#define TOPS_CLUST0_CX_TO_AP_CMD_CLR(x) \
+ (MBOX_CLUST0_BASE + 0x244 + ((x) * 0x200))
+#define TOPS_CLUST0_CM_TO_CX_CMD_SET(x) \
+ (MBOX_CLUST0_BASE + 0x900 + ((x) * 0x40))
+#define TOPS_CLUST0_CM_TO_CX_CMD_CLR(x) \
+ (MBOX_CLUST0_BASE + 0x904 + ((x) * 0x40))
+#define TOPS_CLUST0_AP_TO_CX_CMD_SET(x) \
+ (MBOX_CLUST0_BASE + 0xB00 + ((x) * 0x40))
+#define TOPS_CLUST0_AP_TO_CX_CMD_CLR(x) \
+ (MBOX_CLUST0_BASE + 0xB04 + ((x) * 0x40))
+
+#define TOPS_CLUST0_CX_TO_CY_MSG_N(x, y, n) \
+ (MBOX_CLUST0_BASE + 0x108 + ((n) * 0x4) + ((x) * 0x200) + ((y) * 0x40))
+#define TOPS_CLUST0_CX_TO_CM_MSG_N(x, n) \
+ (MBOX_CLUST0_BASE + 0x208 + ((n) * 0x4) + ((x) * 0x200))
+#define TOPS_CLUST0_CX_TO_AP_MSG_N(x, n) \
+ (MBOX_CLUST0_BASE + 0x248 + ((n) * 0x4) + ((x) * 0x200))
+#define TOPS_CLUST0_CM_TO_CX_MSG_N(x, n) \
+ (MBOX_CLUST0_BASE + 0x908 + ((n) * 0x4) + ((x) * 0x40))
+#define TOPS_CLUST0_AP_TO_CX_MSG_N(x, n) \
+ (MBOX_CLUST0_BASE + 0xB08 + ((n) * 0x4) + ((x) * 0x40))
+
+#define MBOX_TOP_MBOX_FROM_C0 (0x1)
+#define MBOX_TOP_MBOX_FROM_C1 (0x2)
+#define MBOX_TOP_MBOX_FROM_C2 (0x4)
+#define MBOX_TOP_MBOX_FROM_C3 (0x8)
+#define MBOX_TOP_MBOX_FROM_AP (0x10)
+#define MBOX_TOP_MBOX_FROM_CM (0x20) /* TODO: need DE update */
+
+#define MBOX_CLUST0_MBOX_FROM_C0 (0x1)
+#define MBOX_CLUST0_MBOX_FROM_C1 (0x2)
+#define MBOX_CLUST0_MBOX_FROM_C2 (0x4)
+#define MBOX_CLUST0_MBOX_FROM_C3 (0x8)
+#define MBOX_CLUST0_MBOX_FROM_CM (0x10)
+#define MBOX_CLUST0_MBOX_FROM_AP (0x20)
+
+struct mailbox_msg;
+struct mailbox_dev;
+enum mbox_msg_cnt;
+
+typedef void (*mbox_ret_func_t)(void *priv, struct mailbox_msg *msg);
+typedef enum mbox_msg_cnt (*mbox_handler_func_t)(struct mailbox_dev *mdev,
+ struct mailbox_msg *msg);
+
+enum mbox_act {
+ MBOX_SEND,
+ MBOX_RECV,
+ MBOX_ACT_MAX,
+};
+
+enum mbox_msg_cnt {
+ MBOX_NO_RET_MSG,
+ MBOX_RET_MSG1,
+ MBOX_RET_MSG2,
+ MBOX_RET_MSG3,
+ MBOX_RET_MSG4,
+};
+
+struct mailbox_msg {
+ u32 msg1;
+ u32 msg2;
+ u32 msg3;
+ u32 msg4;
+};
+
+struct mailbox_dev {
+ struct list_head list;
+ enum core_id core;
+ mbox_handler_func_t mbox_handler;
+ void *priv;
+ u8 cmd_id;
+};
+
+int mbox_send_msg_no_wait_irq(struct mailbox_dev *mdev, struct mailbox_msg *msg);
+int mbox_send_msg_no_wait(struct mailbox_dev *mdev, struct mailbox_msg *msg);
+int mbox_send_msg(struct mailbox_dev *mdev, struct mailbox_msg *msg, void *priv,
+ mbox_ret_func_t ret_handler);
+int register_mbox_dev(enum mbox_act act, struct mailbox_dev *mdev);
+int unregister_mbox_dev(enum mbox_act act, struct mailbox_dev *mdev);
+void mtk_tops_mbox_clear_all_cmd(void);
+int mtk_tops_mbox_init(void);
+void mtk_tops_mbox_exit(void);
+#endif /* _TOPS_MBOX_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/mbox_id.h b/package-21.02/kernel/tops/src/inc/mbox_id.h
new file mode 100644
index 0000000..bb46250
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/mbox_id.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_MBOX_ID_H_
+#define _TOPS_MBOX_ID_H_
+
+enum mbox_cm2ap_cmd_id {
+ MBOX_CM2AP_CMD_CORE_CTRL = 0,
+ MBOX_CM2AP_CMD_HPDMA = 10,
+ MBOX_CM2AP_CMD_TNL_OFFLOAD = 11,
+ MBOX_CM2AP_CMD_TEST = 31,
+ __MBOX_CM2AP_CMD_MAX = 32,
+};
+
+enum mbox_ap2cm_cmd_id {
+ MBOX_AP2CM_CMD_CORE_CTRL = 0,
+ MBOX_AP2CM_CMD_NET = 1,
+ MBOX_AP2CM_CMD_WDT = 2,
+ MBOX_AP2CM_CMD_TNL_OFFLOAD = 11,
+ MBOX_AP2CM_CMD_TEST = 31,
+ __MBOX_AP2CM_CMD_MAX = 32,
+};
+
+enum mbox_cx2ap_cmd_id {
+ MBOX_CX2AP_CMD_CORE_CTRL = 0,
+ MBOX_CX2AP_CMD_HPDMA = 10,
+ __MBOX_CX2AP_CMD_MAX = 32,
+};
+
+enum mbox_ap2cx_cmd_id {
+ MBOX_AP2CX_CMD_CORE_CTRL = 0,
+ MBOX_AP2CX_CMD_NET = 1,
+ MBOX_AP2CX_CMD_WDT = 2,
+ __MBOX_AP2CX_CMD_MAX = 32,
+};
+
+enum mbox_cm2cx_cmd_id {
+ MBOX_CM2CX_CMD_CORE_CTRL = 0,
+ __MBOX_CM2CX_CMD_MAX = 32,
+};
+
+enum mbox_cx2cm_cmd_id {
+ MBOX_CX2CM_CMD_CORE_CTRL = 0,
+ __MBOX_CX2CM_CMD_MAX = 32,
+};
+
+#endif /* _TOPS_MBOX_ID_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/mcu.h b/package-21.02/kernel/tops/src/inc/mcu.h
new file mode 100644
index 0000000..7c463eb
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/mcu.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_MCU_H_
+#define _TOPS_MCU_H_
+
+#include <linux/clk.h>
+#include <linux/bits.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/timer.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+#include "tops.h"
+
+struct mcu_state;
+
+#define TOP_CORE_BASE (0x001000)
+#define TOP_SEC_BASE (0x00A000)
+#define TOP_L2SRAM (0x100000)
+#define TOP_CORE_M_DTCM (0x300000)
+#define TOP_CORE_M_ITCM (0x310000)
+#define CLUST_CORE_BASE(x) (0x501000 + 0x1000 * (x))
+#define CLUST_SEC_BASE (0x50A000)
+#define CLUST_L2SRAM (0x700000)
+#define CLUST_CORE_X_DTCM(x) (0x800000 + 0x20000 * (x))
+#define CLUST_CORE_X_ITCM(x) (0x810000 + 0x20000 * (x))
+
+/* CORE */
+#define TOP_CORE_NPU_SW_RST (TOP_CORE_BASE + 0x00)
+#define TOP_CORE_NPU_CTRL (TOP_CORE_BASE + 0x04)
+#define TOP_CORE_OCD_CTRL (TOP_CORE_BASE + 0x18)
+
+#define TOP_CORE_DBG_CTRL (TOP_SEC_BASE + 0x64)
+#define TOP_CORE_M_STAT_VECTOR_SEL (TOP_SEC_BASE + 0x68)
+#define TOP_CORE_M_RESET_VECTOR (TOP_SEC_BASE + 0x6C)
+
+#define CLUST_CORE_NPU_SW_RST(x) (CLUST_CORE_BASE(x) + 0x00)
+#define CLUST_CORE_NPU_CTRL(x) (CLUST_CORE_BASE(x) + 0x04)
+#define CLUST_CORE_OCD_CTRL(x) (CLUST_CORE_BASE(x) + 0x18)
+
+#define CLUST_CORE_DBG_CTRL (CLUST_SEC_BASE + 0x64)
+#define CLUST_CORE_X_STAT_VECTOR_SEL(x) (CLUST_SEC_BASE + 0x68 + (0xC * (x)))
+#define CLUST_CORE_X_RESET_VECTOR(x) (CLUST_SEC_BASE + 0x6C + (0xC * (x)))
+
+#define MCU_ACT_ABNORMAL (BIT(MCU_ACT_ABNORMAL_BIT))
+#define MCU_ACT_RESET (BIT(MCU_ACT_RESET_BIT))
+#define MCU_ACT_NETSTOP (BIT(MCU_ACT_NETSTOP_BIT))
+#define MCU_ACT_SHUTDOWN (BIT(MCU_ACT_SHUTDOWN_BIT))
+#define MCU_ACT_INIT (BIT(MCU_ACT_INIT_BIT))
+#define MCU_ACT_STALL (BIT(MCU_ACT_STALL_BIT))
+#define MCU_ACT_FREERUN (BIT(MCU_ACT_FREERUN_BIT))
+
+#define MCU_CTRL_ARG_NUM 2
+
+enum mcu_act {
+ MCU_ACT_ABNORMAL_BIT,
+ MCU_ACT_RESET_BIT,
+ MCU_ACT_NETSTOP_BIT,
+ MCU_ACT_SHUTDOWN_BIT,
+ MCU_ACT_INIT_BIT,
+ MCU_ACT_STALL_BIT,
+ MCU_ACT_FREERUN_BIT,
+
+ __MCU_ACT_MAX,
+};
+
+enum mcu_state_type {
+ MCU_STATE_TYPE_SHUTDOWN,
+ MCU_STATE_TYPE_INIT,
+ MCU_STATE_TYPE_FREERUN,
+ MCU_STATE_TYPE_STALL,
+ MCU_STATE_TYPE_NETSTOP,
+ MCU_STATE_TYPE_RESET,
+ MCU_STATE_TYPE_ABNORMAL,
+
+ __MCU_STATE_TYPE_MAX,
+};
+
+enum mcu_cmd_type {
+ MCU_CMD_TYPE_NULL,
+ MCU_CMD_TYPE_INIT_DONE,
+ MCU_CMD_TYPE_STALL,
+ MCU_CMD_TYPE_STALL_DONE,
+ MCU_CMD_TYPE_FREERUN,
+ MCU_CMD_TYPE_FREERUN_DONE,
+ MCU_CMD_TYPE_ASSERT_RESET,
+ MCU_CMD_TYPE_ASSERT_RESET_DONE,
+ MCU_CMD_TYPE_RELEASE_RESET,
+ MCU_CMD_TYPE_RELEASE_RESET_DONE,
+
+ __MCU_CMD_TYPE_MAX,
+};
+
+enum mcu_event_type {
+ MCU_EVENT_TYPE_NULL,
+ MCU_EVENT_TYPE_SYNC_TNL,
+ MCU_EVENT_TYPE_WDT_TIMEOUT,
+ MCU_EVENT_TYPE_FE_RESET,
+
+ __MCU_EVENT_TYPE_MAX,
+};
+
+struct mcu_ctrl_cmd {
+ enum mcu_event_type e;
+ u32 arg[MCU_CTRL_ARG_NUM];
+ /*
+ * if bit n (BIT(enum core_id)) == 1, send control message to that core.
+ * default send to all cores if core_mask == 0
+ */
+ u32 core_mask;
+};
+
+struct mcu_state {
+ enum mcu_state_type state;
+ struct mcu_state *(*state_trans)(u32 mcu_act, struct mcu_state *state);
+ int (*enter)(struct mcu_state *state);
+ int (*leave)(struct mcu_state *state);
+};
+
+bool mtk_tops_mcu_alive(void);
+bool mtk_tops_mcu_bring_up_done(void);
+bool mtk_tops_mcu_netsys_fe_rst(void);
+int mtk_tops_mcu_stall(struct mcu_ctrl_cmd *mcmd,
+ void (*callback)(void *param), void *param);
+int mtk_tops_mcu_reset(struct mcu_ctrl_cmd *mcmd,
+ void (*callback)(void *param), void *param);
+
+int mtk_tops_mcu_bring_up(struct platform_device *pdev);
+void mtk_tops_mcu_tear_down(struct platform_device *pdev);
+int mtk_tops_mcu_init(struct platform_device *pdev);
+void mtk_tops_mcu_deinit(struct platform_device *pdev);
+#endif /* _TOPS_MCU_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/net-event.h b/package-21.02/kernel/tops/src/inc/net-event.h
new file mode 100644
index 0000000..785a124
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/net-event.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_NET_EVENT_H_
+#define _TOPS_NET_EVENT_H_
+
+#include <linux/platform_device.h>
+
+#include <mtk_eth_soc.h>
+#include <mtk_eth_reset.h>
+
+struct tops_net_ser_data {
+ struct net_device *ndev;
+};
+
+int mtk_tops_netevent_register(struct platform_device *pdev);
+void mtk_tops_netevent_unregister(struct platform_device *pdev);
+#endif /* _TOPS_NET_EVENT_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/netsys.h b/package-21.02/kernel/tops/src/inc/netsys.h
new file mode 100644
index 0000000..1f51695
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/netsys.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_NETSYS_H_
+#define _TOPS_NETSYS_H_
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/platform_device.h>
+
+#include "tunnel.h"
+
+/* FE BASE */
+#define FE_BASE (0x0000)
+
+/* PPE BASE */
+#define PPE0_BASE (0x2000)
+#define PPE1_BASE (0x2400)
+#define PPE2_BASE (0x2C00)
+
+/* FE_INT */
+#define FE_INT_GRP (0x0020)
+#define FE_INT_STA2 (0x0028)
+#define FE_INT_EN2 (0x002C)
+
+/* PSE IQ/OQ */
+#define PSE_IQ_STA6 (0x0194)
+#define PSE_OQ_STA6 (0x01B4)
+
+/* PPE */
+#define PPE_TBL_CFG (0x021C)
+
+/* FE_INT_GRP */
+#define FE_MISC_INT_ASG_SHIFT (0)
+#define FE_MISC_INT_ASG_MASK GENMASK(3, 0)
+
+/* FE_INT_STA2/FE_INT_EN2 */
+#define PSE_FC_ON_1_SHIFT (0)
+#define PSE_FC_ON_1_MASK GENMASK(6, 0)
+#define TDMA_TX_PAUSE (BIT(2))
+
+/* PSE IQ/OQ PORT */
+#define TDMA_PORT_SHIFT (0)
+#define TDMA_PORT_MASK GENMASK(15, 0)
+
+u32 mtk_tops_netsys_ppe_get_max_entry_num(u32 ppe_id);
+int mtk_tops_netsys_init(struct platform_device *pdev);
+void mtk_tops_netsys_deinit(struct platform_device *pdev);
+#endif /* _TOPS_NETSYS_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/ser.h b/package-21.02/kernel/tops/src/inc/ser.h
new file mode 100644
index 0000000..99f9d3d
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/ser.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Alvin Kuo <alvin.kuog@mediatek.com>
+ */
+
+#ifndef _TOPS_SER_H_
+#define _TOPS_SER_H_
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+
+#include "net-event.h"
+#include "mcu.h"
+#include "wdt.h"
+
+enum tops_ser_type {
+ TOPS_SER_NETSYS_FE_RST,
+ TOPS_SER_WDT_TO,
+
+ __TOPS_SER_TYPE_MAX,
+};
+
+struct tops_ser_params {
+ enum tops_ser_type type;
+
+ union {
+ struct tops_net_ser_data net;
+ struct tops_wdt_ser_data wdt;
+ } data;
+
+ void (*ser_callback)(struct tops_ser_params *ser_params);
+ void (*ser_mcmd_setup)(struct tops_ser_params *ser_params,
+ struct mcu_ctrl_cmd *mcmd);
+};
+
+int mtk_tops_ser(struct tops_ser_params *ser_params);
+int mtk_tops_ser_init(struct platform_device *pdev);
+int mtk_tops_ser_deinit(struct platform_device *pdev);
+#endif /* _TOPS_SER_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/tdma.h b/package-21.02/kernel/tops/src/inc/tdma.h
new file mode 100644
index 0000000..2cbd644
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/tdma.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_TDMA_H_
+#define _TOPS_TDMA_H_
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+/* TDMA */
+#define TDMA_BASE (0x6000)
+
+#define TDMA_TX_CTX_IDX_0 (0x008)
+#define TDMA_RX_MAX_CNT_X(idx) (0x104 + ((idx) * 0x10))
+#define TDMA_RX_CRX_IDX_X(idx) (0x108 + ((idx) * 0x10))
+#define TDMA_RX_DRX_IDX_X(idx) (0x10C + ((idx) * 0x10))
+#define TDMA_GLO_CFG0 (0x204)
+#define TDMA_RST_IDX (0x208)
+#define TDMA_TX_XDMA_FIFO_CFG0 (0x238)
+#define TDMA_RX_XDMA_FIFO_CFG0 (0x23C)
+#define TDMA_PREF_TX_CFG (0x2D0)
+#define TDMA_PREF_TX_FIFO_CFG0 (0x2D4)
+#define TDMA_PREF_RX_CFG (0x2DC)
+#define TDMA_PREF_RX_FIFO_CFG0 (0x2E0)
+#define TDMA_PREF_SIDX_CFG (0x2E4)
+#define TDMA_WRBK_TX_CFG (0x300)
+#define TDMA_WRBK_TX_FIFO_CFG0 (0x304)
+#define TDMA_WRBK_RX_CFG (0x344)
+#define TDMA_WRBK_RX_FIFO_CFGX(x) (0x348 + 0x4 * (x))
+#define TDMA_WRBK_SIDX_CFG (0x388)
+#define TDMA_PREF_RX_FIFO_CFG1 (0x3EC)
+
+/* TDMA_GLO_CFG0 */
+#define TX_DMA_EN (BIT(0))
+#define TX_DMA_BUSY (BIT(1))
+#define RX_DMA_EN (BIT(2))
+#define RX_DMA_BUSY (BIT(3))
+#define DMA_BT_SIZE_MASK (0x7)
+#define DMA_BT_SIZE_SHIFT (11)
+#define OTSD_THRES_MASK (0xF)
+#define OTSD_THRES_SHIFT (14)
+#define CDM_FCNT_THRES_MASK (0xF)
+#define CDM_FCNT_THRES_SHIFT (18)
+#define LB_MODE (BIT(24))
+#define PKT_WCOMP (BIT(27))
+#define DEC_WCOMP (BIT(28))
+
+/* TDMA_RST_IDX */
+#define RST_DTX_IDX_0 (BIT(0))
+#define RST_DRX_IDX_X(idx) (BIT(16 + (idx)))
+
+/* TDMA_TX_XDMA_FIFO_CFG0 TDMA_RX_XDMA_FIFO_CFG0 */
+#define PAR_FIFO_CLEAR (BIT(0))
+#define CMD_FIFO_CLEAR (BIT(4))
+#define DMAD_FIFO_CLEAR (BIT(8))
+#define ARR_FIFO_CLEAR (BIT(12))
+#define LEN_FIFO_CLEAR (BIT(15))
+#define WID_FIFO_CLEAR (BIT(18))
+#define BID_FIFO_CLEAR (BIT(21))
+
+/* TDMA_SDL_CFG */
+#define SDL_EN (BIT(16))
+#define SDL_MASK (0xFFFF)
+#define SDL_SHIFT (0)
+
+/* TDMA_PREF_TX_CFG TDMA_PREF_RX_CFG */
+#define PREF_BUSY BIT(1)
+#define PREF_EN BIT(0)
+
+/* TDMA_PREF_TX_FIFO_CFG0 TDMA_PREF_RX_FIFO_CFG0 TDMA_PREF_RX_FIFO_CFG1 */
+#define PREF_TX_RING0_CLEAR (BIT(0))
+#define PREF_RX_RINGX_CLEAR(x) (BIT((((x) % 2) * 16)))
+#define PREF_RX_RING1_CLEAR (BIT(0))
+#define PREF_RX_RING2_CLEAR (BIT(16))
+#define PREF_RX_RING3_CLEAR (BIT(0))
+#define PREF_RX_RING4_CLEAR (BIT(16))
+
+/* TDMA_PREF_SIDX_CFG TDMA_WRBK_SIDX_CFG */
+#define TX_RING0_SIDX_CLR (BIT(0))
+#define RX_RINGX_SIDX_CLR(x) (BIT(4 + (x)))
+
+/* TDMA_WRBK_TX_FIFO_CFG0 TDMA_WRBK_RX_FIFO_CFGX */
+#define WRBK_RING_CLEAR (BIT(0))
+
+/* TDMA_WRBK_TX_CFG TDMA_WRBK_RX_CFG */
+#define WRBK_BUSY (BIT(0))
+#define BURST_SIZE_SHIFT (6)
+#define BURST_SIZE_MASK (0x1F)
+#define WRBK_THRES_SHIFT (14)
+#define WRBK_THRES_MASK (0x3F)
+#define FLUSH_TIMER_EN (BIT(21))
+#define MAX_PENDING_TIME_SHIFT (22)
+#define MAX_PENDING_TIME_MASK (0xFF)
+#define WRBK_EN (BIT(30))
+
+#define TDMA_RING_NUM (4)
+#define TDMA_RING_NUM_MOD (TDMA_RING_NUM - 1)
+
+enum tops_net_cmd {
+ TOPS_NET_CMD_NULL,
+ TOPS_NET_CMD_STOP,
+ TOPS_NET_CMD_START,
+
+ __TOPS_NET_CMD_MAX,
+};
+
+void mtk_tops_tdma_record_last_state(void);
+void mtk_tops_tdma_reset(void);
+int mtk_tops_tdma_enable(void);
+void mtk_tops_tdma_disable(void);
+int mtk_tops_tdma_init(struct platform_device *pdev);
+void mtk_tops_tdma_deinit(struct platform_device *pdev);
+#endif /* _TOPS_TDMA_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/tops.h b/package-21.02/kernel/tops/src/inc/tops.h
new file mode 100644
index 0000000..224ed7f
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/tops.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_H_
+#define _TOPS_H_
+
+#define CORE_TOPS_MASK (GENMASK(CORE_TOPS_NUM - 1, 0))
+
+enum core_id {
+ CORE_OFFLOAD_0,
+ CORE_OFFLOAD_1,
+ CORE_OFFLOAD_2,
+ CORE_OFFLOAD_3,
+ CORE_OFFLOAD_NUM,
+ CORE_MGMT = CORE_OFFLOAD_NUM,
+ CORE_TOPS_NUM,
+ CORE_AP = CORE_TOPS_NUM,
+ CORE_MAX,
+};
+#endif /* _TOPS_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/trm-fs.h b/package-21.02/kernel/tops/src/inc/trm-fs.h
new file mode 100644
index 0000000..972924f
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/trm-fs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Alvin Kuo <alvin.kuog@mediatek.com>
+ * Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_TRM_FS_H_
+#define _TOPS_TRM_FS_H_
+
+#define RLY_DUMP_SUBBUF_SZ 2048
+#define RLY_DUMP_SUBBUF_NUM 256
+
+bool mtk_trm_fs_is_init(void);
+void *mtk_trm_fs_relay_reserve(u32 size);
+void mtk_trm_fs_relay_flush(void);
+int mtk_trm_fs_init(void);
+void mtk_trm_fs_deinit(void);
+#endif /* _TOPS_TRM_FS_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/trm-mcu.h b/package-21.02/kernel/tops/src/inc/trm-mcu.h
new file mode 100644
index 0000000..e3f9e3f
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/trm-mcu.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Alvin Kuo <alvin.kuog@mediatek.com>
+ * Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_TRM_MCU_H_
+#define _TOPS_TRM_MCU_H_
+
+#include "tops.h"
+
+#define XCHAL_NUM_AREG (32)
+#define CORE_DUMP_FRAM_MAGIC (0x00BE00BE)
+
+#define CORE_DUMP_FRAME_LEN (sizeof(struct core_dump_fram))
+
+/* need to sync with core_dump.S */
+struct core_dump_fram {
+ uint32_t magic;
+ uint32_t num_areg;
+ uint32_t pc;
+ uint32_t ps;
+ uint32_t windowstart;
+ uint32_t windowbase;
+ uint32_t epc1;
+ uint32_t exccause;
+ uint32_t excvaddr;
+ uint32_t excsave1;
+ uint32_t areg[XCHAL_NUM_AREG];
+};
+
+extern struct core_dump_fram cd_frams[CORE_TOPS_NUM];
+
+int mtk_trm_mcu_core_dump(void);
+int mtk_tops_trm_mcu_init(void);
+void mtk_tops_trm_mcu_exit(void);
+#endif /* _TOPS_TRM_MCU_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/trm.h b/package-21.02/kernel/tops/src/inc/trm.h
new file mode 100644
index 0000000..4b5118f
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/trm.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Alvin Kuo <alvin.kuog@mediatek.com>
+ * Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_TRM_H_
+#define _TOPS_TRM_H_
+
+#include <linux/platform_device.h>
+
+extern struct device *trm_dev;
+
+#define TRM_DBG(fmt, ...) dev_dbg(trm_dev, "[TRM] " fmt, ##__VA_ARGS__)
+#define TRM_INFO(fmt, ...) dev_info(trm_dev, "[TRM] " fmt, ##__VA_ARGS__)
+#define TRM_NOTICE(fmt, ...) dev_notice(trm_dev, "[TRM] " fmt, ##__VA_ARGS__)
+#define TRM_WARN(fmt, ...) dev_warn(trm_dev, "[TRM] " fmt, ##__VA_ARGS__)
+#define TRM_ERR(fmt, ...) dev_err(trm_dev, "[TRM] " fmt, ##__VA_ARGS__)
+
+#define TRM_CONFIG_NAME_MAX_LEN 32
+
+/* TRM Configuration */
+#define TRM_CFG(_name, _addr, _len, _ofs, _size, _flag) \
+ .name = _name, \
+ .addr = _addr, \
+ .len = _len, \
+ .offset = _ofs, \
+ .size = _size, \
+ .flag = _flag,
+
+#define TRM_CFG_EN(name, addr, len, ofs, size, flag) \
+ TRM_CFG(name, addr, len, ofs, size, TRM_CONFIG_F_ENABLE | (flag))
+
+#define TRM_CFG_CORE_DUMP_EN(name, addr, len, ofs, size, flag, core_id) \
+ TRM_CFG_EN(name, addr, len, ofs, size, TRM_CONFIG_F_CORE_DUMP | flag) \
+ .core = core_id
+
+/* TRM configuration flags */
+#define TRM_CONFIG_F(trm_cfg_bit) \
+ (BIT(TRM_CONFIG_F_ ## trm_cfg_bit ## _BIT))
+#define TRM_CONFIG_F_CX_CORE_DUMP_MASK (GENMASK(CORE_TOPS_NUM, 0))
+#define TRM_CONFIG_F_CX_CORE_DUMP_SHIFT (0)
+
+/* TRM reason flag */
+#define TRM_RSN(trm_rsn_bit) (BIT(TRM_RSN_ ## trm_rsn_bit ## _BIT))
+
+/* TRM Reason */
+#define TRM_RSN_NULL (0x0000)
+#define TRM_RSN_WDT_TIMEOUT_CORE0 (TRM_RSN(C0_WDT))
+#define TRM_RSN_WDT_TIMEOUT_CORE1 (TRM_RSN(C1_WDT))
+#define TRM_RSN_WDT_TIMEOUT_CORE2 (TRM_RSN(C2_WDT))
+#define TRM_RSN_WDT_TIMEOUT_CORE3 (TRM_RSN(C3_WDT))
+#define TRM_RSN_WDT_TIMEOUT_COREM (TRM_RSN(CM_WDT))
+#define TRM_RSN_FE_RESET (TRM_RSN(FE_RESET))
+#define TRM_RSN_MCU_STATE_ACT_FAIL (TRM_RSN(MCU_STATE_ACT_FAIL))
+
+enum trm_config_flag {
+ TRM_CONFIG_F_ENABLE_BIT,
+ TRM_CONFIG_F_CORE_DUMP_BIT,
+};
+
+enum trm_rsn {
+ TRM_RSN_C0_WDT_BIT,
+ TRM_RSN_C1_WDT_BIT,
+ TRM_RSN_C2_WDT_BIT,
+ TRM_RSN_C3_WDT_BIT,
+ TRM_RSN_CM_WDT_BIT,
+ TRM_RSN_FE_RESET_BIT,
+ TRM_RSN_MCU_STATE_ACT_FAIL_BIT,
+};
+
+enum trm_hardware {
+ TRM_TOPS,
+ TRM_NETSYS,
+ TRM_TDMA,
+
+ __TRM_HARDWARE_MAX,
+};
+
+struct trm_config {
+ char name[TRM_CONFIG_NAME_MAX_LEN];
+ enum core_id core; /* valid if TRM_CONFIG_F_CORE_DUMP is set */
+ u32 addr; /* memory address of the dump info */
+ u32 len; /* total length of the dump info */
+ u32 offset; /* dump offset */
+ u32 size; /* dump size */
+ u8 flag;
+#define TRM_CONFIG_F_CORE_DUMP (TRM_CONFIG_F(CORE_DUMP))
+#define TRM_CONFIG_F_ENABLE (TRM_CONFIG_F(ENABLE))
+};
+
+struct trm_hw_config {
+ struct trm_config *trm_cfgs;
+ u32 cfg_len;
+ int (*trm_hw_dump)(void *dst, u32 ofs, u32 len);
+};
+
+int mtk_trm_dump(u32 dump_rsn);
+int mtk_trm_cfg_setup(char *name, u32 offset, u32 size, u8 enable);
+int mtk_tops_trm_init(void);
+void mtk_tops_trm_exit(void);
+int mtk_trm_hw_config_register(enum trm_hardware trm_hw,
+ struct trm_hw_config *trm_hw_cfg);
+void mtk_trm_hw_config_unregister(enum trm_hardware trm_hw,
+ struct trm_hw_config *trm_hw_cfg);
+#endif /* _TOPS_TRM_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/tunnel.h b/package-21.02/kernel/tops/src/inc/tunnel.h
new file mode 100644
index 0000000..961aa03
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/tunnel.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
+ */
+
+#ifndef _TOPS_TUNNEL_H_
+#define _TOPS_TUNNEL_H_
+
+#include <linux/bitmap.h>
+#include <linux/hashtable.h>
+#include <linux/if_ether.h>
+#include <linux/ip.h>
+#include <linux/kthread.h>
+#include <linux/netdevice.h>
+#include <linux/refcount.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "protocol/l2tp/l2tp.h"
+
+/* tunnel info status */
+#define TNL_STA_UNINIT (BIT(TNL_STATUS_UNINIT))
+#define TNL_STA_INIT (BIT(TNL_STATUS_INIT))
+#define TNL_STA_QUEUED (BIT(TNL_STATUS_QUEUED))
+#define TNL_STA_UPDATING (BIT(TNL_STATUS_UPDATING))
+#define TNL_STA_UPDATED (BIT(TNL_STATUS_UPDATED))
+#define TNL_STA_DIP_UPDATE (BIT(TNL_STATUS_DIP_UPDATE))
+#define TNL_STA_DELETING (BIT(TNL_STATUS_DELETING))
+
+/* tunnel params flags */
+#define TNL_DECAP_ENABLE (BIT(TNL_PARAMS_DECAP_ENABLE_BIT))
+#define TNL_ENCAP_ENABLE (BIT(TNL_PARAMS_ENCAP_ENABLE_BIT))
+
+/* tunnel info flags */
+#define TNL_INFO_DEBUG (BIT(TNL_INFO_DEBUG_BIT))
+
+struct tops_tnl_info;
+struct tops_tnl_params;
+
+/*
+ * tops_crsn
+ * TOPS_CRSN_TNL_ID_START
+ * TOPS_CRSN_TNL_ID_END
+ * APMCU checks whether tops_crsn is in this range to know if this packet
+ * was processed by TOPS previously.
+ */
+enum tops_crsn {
+ TOPS_CRSN_IGNORE = 0x00,
+ TOPS_CRSN_TNL_ID_START = 0x10,
+ TOPS_CRSN_TNL_ID_END = 0x2F,
+};
+
+enum tops_entry_type {
+ TOPS_ENTRY_NONE = 0,
+ TOPS_ENTRY_GRETAP,
+ TOPS_ENTRY_PPTP,
+ TOPS_ENTRY_IP_L2TP,
+ TOPS_ENTRY_UDP_L2TP_CTRL,
+ TOPS_ENTRY_UDP_L2TP_DATA = 5,
+ TOPS_ENTRY_VXLAN,
+ TOPS_ENTRY_NATT,
+ TOPS_ENTRY_CAPWAP_CTRL,
+ TOPS_ENTRY_CAPWAP_DATA,
+ TOPS_ENTRY_CAPWAP_DTLS = 10,
+ TOPS_ENTRY_IPSEC_ESP,
+ TOPS_ENTRY_IPSEC_AH,
+
+ __TOPS_ENTRY_MAX = CONFIG_TOPS_TNL_NUM,
+};
+
+enum tops_tunnel_mbox_cmd {
+ TOPS_TNL_MBOX_CMD_RESV,
+ TOPS_TNL_START_ADDR_SYNC,
+
+ __TOPS_TNL_MBOX_CMD_MAX,
+};
+
+enum tunnel_ctrl_event {
+ TUNNEL_CTRL_EVENT_NULL,
+ TUNNEL_CTRL_EVENT_NEW,
+ TUNNEL_CTRL_EVENT_DEL,
+ TUNNEL_CTRL_EVENT_DIP_UPDATE,
+
+ __TUNNEL_CTRL_EVENT_MAX,
+};
+
+enum tnl_status {
+ TNL_STATUS_UNINIT,
+ TNL_STATUS_INIT,
+ TNL_STATUS_QUEUED,
+ TNL_STATUS_UPDATING,
+ TNL_STATUS_UPDATED,
+ TNL_STATUS_DIP_UPDATE,
+ TNL_STATUS_DELETING,
+
+ __TNL_STATUS_MAX,
+};
+
+enum tops_tnl_params_flag {
+ TNL_PARAMS_DECAP_ENABLE_BIT,
+ TNL_PARAMS_ENCAP_ENABLE_BIT,
+};
+
+enum tops_tnl_info_flag {
+ TNL_INFO_DEBUG_BIT,
+};
+
+/* record outer tunnel header data for HW offloading */
+struct tops_tnl_params {
+ u8 daddr[ETH_ALEN];
+ u8 saddr[ETH_ALEN];
+ __be32 dip;
+ __be32 sip;
+ __be16 dport;
+ __be16 sport;
+ u16 protocol;
+ u8 tops_entry_proto;
+ u8 flag; /* bit: enum tops_tnl_params_flag */
+ union {
+ struct l2tp_param l2tp; /* 4B */
+ } priv;
+} __packed __aligned(16);
+
+struct tops_tnl_info {
+ struct tops_tnl_params tnl_params;
+ struct tops_tnl_params cache;
+ struct list_head sync_node;
+ struct hlist_node hlist;
+ struct net_device *dev;
+ struct timer_list taging;
+ spinlock_t lock;
+ u32 tnl_idx;
+ u32 status;
+ u32 flag; /* bit: enum tops_tnl_info_flag */
+ refcount_t refcnt;
+} __aligned(16);
+
+struct tops_tnl_type {
+ const char *type_name;
+ int (*tnl_decap_param_setup)(struct sk_buff *skb,
+ struct tops_tnl_params *tnl_params);
+ int (*tnl_encap_param_setup)(struct sk_buff *skb,
+ struct tops_tnl_params *tnl_params);
+ int (*tnl_debug_param_setup)(const char *buf, int *ofs,
+ struct tops_tnl_params *tnl_params);
+ int (*tnl_dump_param)(char *buf, struct tops_tnl_params *tnl_params);
+ bool (*tnl_info_match)(struct tops_tnl_params *params1,
+ struct tops_tnl_params *params2);
+ bool (*tnl_decap_offloadable)(struct sk_buff *skb);
+ enum tops_entry_type tops_entry;
+ bool has_inner_eth;
+};
+
+void mtk_tops_tnl_info_submit_no_tnl_lock(struct tops_tnl_info *tnl_info);
+void mtk_tops_tnl_info_submit(struct tops_tnl_info *tnl_info);
+struct tops_tnl_info *mtk_tops_tnl_info_find(struct tops_tnl_params *tnl_params);
+struct tops_tnl_info *mtk_tops_tnl_info_alloc(void);
+void mtk_tops_tnl_info_hash(struct tops_tnl_info *tnl_info);
+
+int mtk_tops_tnl_offload_init(struct platform_device *pdev);
+void mtk_tops_tnl_offload_deinit(struct platform_device *pdev);
+int mtk_tops_tnl_offload_proto_setup(struct platform_device *pdev);
+void mtk_tops_tnl_offload_proto_teardown(struct platform_device *pdev);
+void mtk_tops_tnl_offload_flush(void);
+void mtk_tops_tnl_offload_recover(void);
+void mtk_tops_tnl_offload_netdev_down(struct net_device *ndev);
+
+struct tops_tnl_type *mtk_tops_tnl_type_get_by_name(const char *name);
+int mtk_tops_tnl_type_register(struct tops_tnl_type *tnl_type);
+void mtk_tops_tnl_type_unregister(struct tops_tnl_type *tnl_type);
+#endif /* _TOPS_TUNNEL_H_ */
diff --git a/package-21.02/kernel/tops/src/inc/wdt.h b/package-21.02/kernel/tops/src/inc/wdt.h
new file mode 100644
index 0000000..b70bf63
--- /dev/null
+++ b/package-21.02/kernel/tops/src/inc/wdt.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Alvin Kuo <alvin.kuog@mediatek.com>
+ */
+
+#ifndef _TOPS_WDT_H_
+#define _TOPS_WDT_H_
+
+#include <linux/platform_device.h>
+
+#include "tops.h"
+
+enum wdt_cmd {
+ WDT_CMD_TRIGGER_TIMEOUT,
+
+ __WDT_CMD_MAX,
+};
+
+struct tops_wdt_ser_data {
+ u32 timeout_cores;
+};
+
+int mtk_tops_wdt_trigger_timeout(enum core_id core);
+int mtk_tops_wdt_init(struct platform_device *pdev);
+int mtk_tops_wdt_deinit(struct platform_device *pdev);
+#endif /* _TOPS_WDT_H_ */