blob: ee9e343eeb296f64f637b7bdcf05c68548dd4e69 [file] [log] [blame]
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2023 MediaTek Inc. All Rights Reserved.
*
* Author: Ren-Ting Wang <ren-ting.wang@mediatek.com>
*/
#ifndef _TOPS_HWSPIN_LOCK_H_
#define _TOPS_HWSPIN_LOCK_H_
#include <linux/types.h>
#include "mbox.h"
#define HWSPINLOCK_SLOT_MAX 16
#define HWSPINLOCK_TOP_BASE 0x10100
#define HWSPINLOCK_CLUST_BASE 0x880000
enum hwspinlock_group {
HWSPINLOCK_GROUP_TOP,
HWSPINLOCK_GROUP_CLUST,
__HWSPINLOCK_GROUP_MAX,
};
enum hwspinlock_top_slot {
HWSPINLOCK_TOP_SLOT_HPDMA_LOCK,
HWSPINLOCK_TOP_SLOT_HPDMA_PCH0,
HWSPINLOCK_TOP_SLOT_HPDMA_PCH1,
HWSPINLOCK_TOP_SLOT_HPDMA_PCH2,
HWSPINLOCK_TOP_SLOT_HPDMA_PCH3,
HWSPINLOCK_TOP_SLOT_5,
HWSPINLOCK_TOP_SLOT_6,
HWSPINLOCK_TOP_SLOT_7,
HWSPINLOCK_TOP_SLOT_8,
HWSPINLOCK_TOP_SLOT_9,
HWSPINLOCK_TOP_SLOT_10,
HWSPINLOCK_TOP_SLOT_11,
HWSPINLOCK_TOP_SLOT_12,
HWSPINLOCK_TOP_SLOT_13,
HWSPINLOCK_TOP_SLOT_14,
HWSPINLOCK_TOP_SLOT_15,
__HWSPINLOCK_TOP_MAX = HWSPINLOCK_SLOT_MAX,
};
enum hwspinlock_clust_slot {
HWSPINLOCK_CLUST_SLOT_PRINTF,
HWSPINLOCK_CLUST_SLOT_HPDMA_LOCK,
HWSPINLOCK_CLUST_SLOT_HPDMA_PCH0,
HWSPINLOCK_CLUST_SLOT_HPDMA_PCH1,
HWSPINLOCK_CLUST_SLOT_HPDMA_PCH2,
HWSPINLOCK_CLUST_SLOT_HPDMA_PCH3,
HWSPINLOCK_CLUST_SLOT_6,
HWSPINLOCK_CLUST_SLOT_7,
HWSPINLOCK_CLUST_SLOT_8,
HWSPINLOCK_CLUST_SLOT_9,
HWSPINLOCK_CLUST_SLOT_10,
HWSPINLOCK_CLUST_SLOT_11,
HWSPINLOCK_CLUST_SLOT_12,
HWSPINLOCK_CLUST_SLOT_13,
HWSPINLOCK_CLUST_SLOT_14,
HWSPINLOCK_CLUST_SLOT_15,
__HWSPINLOCK_CLUST_MAX = HWSPINLOCK_SLOT_MAX,
};
int mtk_tops_hwspin_try_lock(enum hwspinlock_group grp, u32 slot);
void mtk_tops_hwspin_lock(enum hwspinlock_group grp, u32 slot);
void mtk_tops_hwspin_unlock(enum hwspinlock_group grp, u32 slot);
int mtk_tops_hwspinlock_init(struct platform_device *pdev);
#endif /* _TOPS_HWSPIN_LOCK_H_ */