blob: dd02baf3565101eb67893fc3a178345ee418be9c [file] [log] [blame]
developerf9a2c032021-09-30 17:18:10 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-snfi-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
7 compatible = "mediatek,mt7986b-snfi-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080053
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
developer283fc452022-08-18 19:50:33 +080058 };
developerf9a2c032021-09-30 17:18:10 +080059 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080065 phy-handle = <&phy6>;
developerf9a2c032021-09-30 17:18:10 +080066 };
67
68 mdio: mdio-bus {
69 #address-cells = <1>;
70 #size-cells = <0>;
71
developerf0a1e452022-08-15 12:06:11 +080072 reset-gpios = <&pio 6 1>;
73 reset-delay-us = <600>;
74
developerf9a2c032021-09-30 17:18:10 +080075 phy5: phy@5 {
developere0c42a12022-08-19 11:01:38 +080076 compatible = "ethernet-phy-ieee802.3-c45";
developerf9a2c032021-09-30 17:18:10 +080077 reg = <5>;
developerf9a2c032021-09-30 17:18:10 +080078 };
79
80 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080081 compatible = "ethernet-phy-ieee802.3-c45";
developerf9a2c032021-09-30 17:18:10 +080082 reg = <6>;
developerf9a2c032021-09-30 17:18:10 +080083 };
84
85 switch@0 {
86 compatible = "mediatek,mt7531";
87 reg = <31>;
88 reset-gpios = <&pio 5 0>;
89
90 ports {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 port@0 {
95 reg = <0>;
96 label = "lan0";
97 };
98
99 port@1 {
100 reg = <1>;
101 label = "lan1";
102 };
103
104 port@2 {
105 reg = <2>;
106 label = "lan2";
107 };
108
109 port@3 {
110 reg = <3>;
111 label = "lan3";
112 };
113
114 port@4 {
115 reg = <4>;
116 label = "lan4";
117 };
118
119 port@5 {
120 reg = <5>;
121 label = "lan5";
122 phy-mode = "2500base-x";
developere0c42a12022-08-19 11:01:38 +0800123 phy-handle = <&phy5>;
developerf9a2c032021-09-30 17:18:10 +0800124 };
125
126 port@6 {
127 reg = <6>;
128 label = "cpu";
129 ethernet = <&gmac0>;
130 phy-mode = "2500base-x";
131
132 fixed-link {
133 speed = <2500>;
134 full-duplex;
135 pause;
136 };
137 };
138 };
139 };
140 };
141};
142
143&hnat {
144 mtketh-wan = "eth1";
145 mtketh-lan = "lan";
146 mtketh-max-gmac = <2>;
147 status = "okay";
148};
149
150/* Warning: pins shared with &uart1 */
151&snand {
152 pinctrl-names = "default";
153 pinctrl-0 = <&snfi_pins>;
154 mediatek,quad-spi;
155 status = "okay";
156
157 partitions {
158 compatible = "fixed-partitions";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 };
162};
163
164/* Warning: pins shared with &uart2 */
165&spi1 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&spic_pins>;
168 status = "okay";
169};
170
171&wbsys {
172 mediatek,mtd-eeprom = <&factory 0x0000>;
173 status = "okay";
174};
175
176&pio {
177 snfi_pins: snfi-pins-23-to-28 {
178 mux {
179 function = "flash";
180 groups = "snfi";
181 };
182 conf-clk {
183 pins = "SPI0_CLK";
184 drive-strength = <MTK_DRIVE_8mA>;
185 mediatek,pull-down-adv = <0>; /* bias-disable */
186 };
187 conf-pu {
188 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
189 drive-strength = <MTK_DRIVE_6mA>;
190 mediatek,pull-up-adv = <0>; /* bias-disable */
191 };
192 conf-pd {
193 pins = "SPI0_MOSI", "SPI0_MISO";
194 drive-strength = <MTK_DRIVE_6mA>;
195 mediatek,pull-down-adv = <0>; /* bias-disable */
196 };
197 };
198};