blob: 436e1225ca7dcc62e73f9041ffb672c7e24ae5ad [file] [log] [blame]
developerf9a2c032021-09-30 17:18:10 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-snfi-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
7 compatible = "mediatek,mt7986b-snfi-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080053
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 link-gpio = <&pio 47 0>;
59 phy-handle = <&phy5>;
60 label = "lan5";
61 };
developerf9a2c032021-09-30 17:18:10 +080062 };
63
64 gmac1: mac@1 {
65 compatible = "mediatek,eth-mac";
66 reg = <1>;
67 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080068 phy-handle = <&phy6>;
developerf9a2c032021-09-30 17:18:10 +080069 };
70
71 mdio: mdio-bus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
developerf0a1e452022-08-15 12:06:11 +080075 reset-gpios = <&pio 6 1>;
76 reset-delay-us = <600>;
77
developerf9a2c032021-09-30 17:18:10 +080078 phy5: phy@5 {
developer283fc452022-08-18 19:50:33 +080079 compatible = "ethernet-phy-id67c9.de0a";
developerf9a2c032021-09-30 17:18:10 +080080 reg = <5>;
developerf9a2c032021-09-30 17:18:10 +080081 };
82
83 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080084 compatible = "ethernet-phy-ieee802.3-c45";
developerf9a2c032021-09-30 17:18:10 +080085 reg = <6>;
developerf9a2c032021-09-30 17:18:10 +080086 };
87
88 switch@0 {
89 compatible = "mediatek,mt7531";
90 reg = <31>;
91 reset-gpios = <&pio 5 0>;
92
93 ports {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 port@0 {
98 reg = <0>;
99 label = "lan0";
100 };
101
102 port@1 {
103 reg = <1>;
104 label = "lan1";
105 };
106
107 port@2 {
108 reg = <2>;
109 label = "lan2";
110 };
111
112 port@3 {
113 reg = <3>;
114 label = "lan3";
115 };
116
117 port@4 {
118 reg = <4>;
119 label = "lan4";
120 };
121
122 port@5 {
123 reg = <5>;
124 label = "lan5";
125 phy-mode = "2500base-x";
126
127 fixed-link {
128 speed = <2500>;
129 full-duplex;
130 pause;
131 };
132 };
133
134 port@6 {
135 reg = <6>;
136 label = "cpu";
137 ethernet = <&gmac0>;
138 phy-mode = "2500base-x";
139
140 fixed-link {
141 speed = <2500>;
142 full-duplex;
143 pause;
144 };
145 };
146 };
147 };
148 };
149};
150
151&hnat {
152 mtketh-wan = "eth1";
153 mtketh-lan = "lan";
154 mtketh-max-gmac = <2>;
155 status = "okay";
156};
157
158/* Warning: pins shared with &uart1 */
159&snand {
160 pinctrl-names = "default";
161 pinctrl-0 = <&snfi_pins>;
162 mediatek,quad-spi;
163 status = "okay";
164
165 partitions {
166 compatible = "fixed-partitions";
167 #address-cells = <1>;
168 #size-cells = <1>;
169 };
170};
171
172/* Warning: pins shared with &uart2 */
173&spi1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&spic_pins>;
176 status = "okay";
177};
178
179&wbsys {
180 mediatek,mtd-eeprom = <&factory 0x0000>;
181 status = "okay";
182};
183
184&pio {
185 snfi_pins: snfi-pins-23-to-28 {
186 mux {
187 function = "flash";
188 groups = "snfi";
189 };
190 conf-clk {
191 pins = "SPI0_CLK";
192 drive-strength = <MTK_DRIVE_8mA>;
193 mediatek,pull-down-adv = <0>; /* bias-disable */
194 };
195 conf-pu {
196 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
197 drive-strength = <MTK_DRIVE_6mA>;
198 mediatek,pull-up-adv = <0>; /* bias-disable */
199 };
200 conf-pd {
201 pins = "SPI0_MOSI", "SPI0_MISO";
202 drive-strength = <MTK_DRIVE_6mA>;
203 mediatek,pull-down-adv = <0>; /* bias-disable */
204 };
205 };
206};