developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986b.dtsi" |
| 3 | #include "mt7986b-pinctrl.dtsi" |
| 4 | #include "mt7986-spim-nand-partition.dtsi" |
| 5 | / { |
| 6 | model = "MediaTek MT7986b RFB"; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 7 | compatible = "mediatek,mt7986b-2500wan-spim-snand-rfb"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 8 | chosen { |
| 9 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 10 | earlycon=uart8250,mmio32,0x11002000"; |
| 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | }; |
| 17 | |
| 18 | &uart0 { |
| 19 | status = "okay"; |
| 20 | }; |
| 21 | |
| 22 | /* Warning: pins shared with &snand */ |
| 23 | &uart1 { |
| 24 | pinctrl-names = "default"; |
| 25 | pinctrl-0 = <&uart1_pins>; |
| 26 | status = "disabled"; |
| 27 | }; |
| 28 | |
| 29 | /* Warning: pins shared with &spi1 */ |
| 30 | &uart2 { |
| 31 | pinctrl-names = "default"; |
| 32 | pinctrl-0 = <&uart2_pins>; |
| 33 | status = "disabled"; |
| 34 | }; |
| 35 | |
| 36 | &i2c0 { |
| 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&i2c_pins>; |
| 39 | status = "okay"; |
| 40 | }; |
| 41 | |
| 42 | &watchdog { |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | |
| 46 | ð { |
| 47 | status = "okay"; |
| 48 | |
| 49 | gmac0: mac@0 { |
| 50 | compatible = "mediatek,eth-mac"; |
| 51 | reg = <0>; |
| 52 | phy-mode = "2500base-x"; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 53 | |
| 54 | fixed-link { |
| 55 | speed = <2500>; |
| 56 | full-duplex; |
| 57 | pause; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 58 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | gmac1: mac@1 { |
| 62 | compatible = "mediatek,eth-mac"; |
| 63 | reg = <1>; |
| 64 | phy-mode = "2500base-x"; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 65 | phy-handle = <&phy6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | mdio: mdio-bus { |
| 69 | #address-cells = <1>; |
| 70 | #size-cells = <0>; |
| 71 | |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 72 | reset-gpios = <&pio 6 1>; |
| 73 | reset-delay-us = <600>; |
| 74 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 75 | phy5: phy@5 { |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 76 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 77 | reg = <5>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | phy6: phy@6 { |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 81 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 82 | reg = <6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | switch@0 { |
| 86 | compatible = "mediatek,mt7531"; |
| 87 | reg = <31>; |
| 88 | reset-gpios = <&pio 5 0>; |
| 89 | |
| 90 | ports { |
| 91 | #address-cells = <1>; |
| 92 | #size-cells = <0>; |
| 93 | |
| 94 | port@0 { |
| 95 | reg = <0>; |
| 96 | label = "lan0"; |
| 97 | }; |
| 98 | |
| 99 | port@1 { |
| 100 | reg = <1>; |
| 101 | label = "lan1"; |
| 102 | }; |
| 103 | |
| 104 | port@2 { |
| 105 | reg = <2>; |
| 106 | label = "lan2"; |
| 107 | }; |
| 108 | |
| 109 | port@3 { |
| 110 | reg = <3>; |
| 111 | label = "lan3"; |
| 112 | }; |
| 113 | |
| 114 | port@4 { |
| 115 | reg = <4>; |
| 116 | label = "lan4"; |
| 117 | }; |
| 118 | |
| 119 | port@5 { |
| 120 | reg = <5>; |
| 121 | label = "lan5"; |
| 122 | phy-mode = "2500base-x"; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 123 | phy-handle = <&phy5>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | port@6 { |
| 127 | reg = <6>; |
| 128 | label = "cpu"; |
| 129 | ethernet = <&gmac0>; |
| 130 | phy-mode = "2500base-x"; |
| 131 | |
| 132 | fixed-link { |
| 133 | speed = <2500>; |
| 134 | full-duplex; |
| 135 | pause; |
| 136 | }; |
| 137 | }; |
| 138 | }; |
| 139 | }; |
| 140 | }; |
| 141 | }; |
| 142 | |
| 143 | &hnat { |
| 144 | mtketh-wan = "eth1"; |
| 145 | mtketh-lan = "lan"; |
| 146 | mtketh-max-gmac = <2>; |
| 147 | status = "okay"; |
| 148 | }; |
| 149 | |
| 150 | &spi0 { |
| 151 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&spi_flash_pins>; |
| 153 | cs-gpios = <0>, <0>; |
| 154 | status = "okay"; |
| 155 | |
| 156 | spi_nor@0 { |
| 157 | #address-cells = <1>; |
| 158 | #size-cells = <1>; |
| 159 | compatible = "jedec,spi-nor"; |
| 160 | reg = <0>; |
developer | a376d36 | 2023-04-11 16:06:53 +0800 | [diff] [blame] | 161 | spi-max-frequency = <52000000>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 162 | spi-tx-buswidth = <4>; |
| 163 | spi-rx-buswidth = <4>; |
| 164 | }; |
| 165 | |
| 166 | spi_nand: spi_nand@1 { |
| 167 | #address-cells = <1>; |
| 168 | #size-cells = <1>; |
| 169 | compatible = "spi-nand"; |
| 170 | reg = <1>; |
developer | a376d36 | 2023-04-11 16:06:53 +0800 | [diff] [blame] | 171 | spi-max-frequency = <52000000>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 172 | spi-tx-buswidth = <4>; |
| 173 | spi-rx-buswidth = <4>; |
| 174 | }; |
| 175 | }; |
| 176 | |
| 177 | /* Warning: pins shared with &uart2 */ |
| 178 | &spi1 { |
| 179 | pinctrl-names = "default"; |
| 180 | pinctrl-0 = <&spic_pins>; |
| 181 | status = "okay"; |
| 182 | }; |
| 183 | |
| 184 | &wbsys { |
| 185 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 186 | status = "okay"; |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 187 | pinctrl-names = "default", "dbdc"; |
| 188 | pinctrl-0 = <&wf_2g_5g_pins>; |
| 189 | pinctrl-1 = <&wf_dbdc_pins>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | &pio { |
| 193 | spi_flash_pins: spi-flash-pins-33-to-38 { |
| 194 | mux { |
| 195 | function = "flash"; |
| 196 | groups = "spi0", "spi0_wp_hold"; |
| 197 | }; |
| 198 | conf-pu { |
| 199 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 200 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 201 | bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 202 | }; |
| 203 | conf-pd { |
| 204 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 205 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 206 | bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 207 | }; |
| 208 | |
| 209 | }; |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 210 | |
| 211 | wf_2g_5g_pins: wf_2g_5g-pins { |
| 212 | mux { |
| 213 | function = "wifi"; |
| 214 | groups = "wf_2g", "wf_5g"; |
| 215 | }; |
| 216 | conf { |
| 217 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 218 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 219 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 220 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 221 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 222 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 223 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 224 | drive-strength = <MTK_DRIVE_4mA>; |
| 225 | }; |
| 226 | }; |
| 227 | |
| 228 | wf_dbdc_pins: wf_dbdc-pins { |
| 229 | mux { |
| 230 | function = "wifi"; |
| 231 | groups = "wf_dbdc"; |
| 232 | }; |
| 233 | conf { |
| 234 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 235 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 236 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 237 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 238 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 239 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 240 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 241 | drive-strength = <MTK_DRIVE_4mA>; |
| 242 | }; |
| 243 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 244 | }; |