blob: 1dcb86344c823c598d2cf6b3de7f2e5d18270ed8 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
developercd6a1382022-01-11 15:45:19 +08007 compatible = "mediatek,mt7986b-2500wan-spim-snand-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080053
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 link-gpio = <&pio 47 0>;
59 phy-handle = <&phy5>;
60 label = "lan5";
61 };
developer565bacb2021-09-28 21:26:32 +080062 };
63
64 gmac1: mac@1 {
65 compatible = "mediatek,eth-mac";
66 reg = <1>;
67 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080068 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +080069 };
70
71 mdio: mdio-bus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
developerf0a1e452022-08-15 12:06:11 +080075 reset-gpios = <&pio 6 1>;
76 reset-delay-us = <600>;
77
developer565bacb2021-09-28 21:26:32 +080078 phy5: phy@5 {
developer283fc452022-08-18 19:50:33 +080079 compatible = "ethernet-phy-id67c9.de0a";
developer565bacb2021-09-28 21:26:32 +080080 reg = <5>;
developer565bacb2021-09-28 21:26:32 +080081 };
82
83 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080084 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +080085 reg = <6>;
developer565bacb2021-09-28 21:26:32 +080086 };
87
88 switch@0 {
89 compatible = "mediatek,mt7531";
90 reg = <31>;
91 reset-gpios = <&pio 5 0>;
92
93 ports {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 port@0 {
98 reg = <0>;
99 label = "lan0";
100 };
101
102 port@1 {
103 reg = <1>;
104 label = "lan1";
105 };
106
107 port@2 {
108 reg = <2>;
109 label = "lan2";
110 };
111
112 port@3 {
113 reg = <3>;
114 label = "lan3";
115 };
116
117 port@4 {
118 reg = <4>;
119 label = "lan4";
120 };
121
122 port@5 {
123 reg = <5>;
124 label = "lan5";
125 phy-mode = "2500base-x";
126
127 fixed-link {
128 speed = <2500>;
129 full-duplex;
130 pause;
131 };
132 };
133
134 port@6 {
135 reg = <6>;
136 label = "cpu";
137 ethernet = <&gmac0>;
138 phy-mode = "2500base-x";
139
140 fixed-link {
141 speed = <2500>;
142 full-duplex;
143 pause;
144 };
145 };
146 };
147 };
148 };
149};
150
151&hnat {
152 mtketh-wan = "eth1";
153 mtketh-lan = "lan";
154 mtketh-max-gmac = <2>;
155 status = "okay";
156};
157
158&spi0 {
159 pinctrl-names = "default";
160 pinctrl-0 = <&spi_flash_pins>;
161 cs-gpios = <0>, <0>;
162 status = "okay";
163
164 spi_nor@0 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "jedec,spi-nor";
168 reg = <0>;
169 spi-max-frequency = <20000000>;
170 spi-tx-buswidth = <4>;
171 spi-rx-buswidth = <4>;
172 };
173
174 spi_nand: spi_nand@1 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 compatible = "spi-nand";
178 reg = <1>;
179 spi-max-frequency = <20000000>;
180 spi-tx-buswidth = <4>;
181 spi-rx-buswidth = <4>;
182 };
183};
184
185/* Warning: pins shared with &uart2 */
186&spi1 {
187 pinctrl-names = "default";
188 pinctrl-0 = <&spic_pins>;
189 status = "okay";
190};
191
192&wbsys {
193 mediatek,mtd-eeprom = <&factory 0x0000>;
194 status = "okay";
developere138bcd2021-12-06 09:20:47 +0800195 pinctrl-names = "default", "dbdc";
196 pinctrl-0 = <&wf_2g_5g_pins>;
197 pinctrl-1 = <&wf_dbdc_pins>;
developer565bacb2021-09-28 21:26:32 +0800198};
199
200&pio {
201 spi_flash_pins: spi-flash-pins-33-to-38 {
202 mux {
203 function = "flash";
204 groups = "spi0", "spi0_wp_hold";
205 };
206 conf-pu {
207 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
208 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800209 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800210 };
211 conf-pd {
212 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
213 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800214 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800215 };
216
217 };
developere138bcd2021-12-06 09:20:47 +0800218
219 wf_2g_5g_pins: wf_2g_5g-pins {
220 mux {
221 function = "wifi";
222 groups = "wf_2g", "wf_5g";
223 };
224 conf {
225 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
226 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
227 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
228 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
229 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
230 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
231 "WF1_TOP_CLK", "WF1_TOP_DATA";
232 drive-strength = <MTK_DRIVE_4mA>;
233 };
234 };
235
236 wf_dbdc_pins: wf_dbdc-pins {
237 mux {
238 function = "wifi";
239 groups = "wf_dbdc";
240 };
241 conf {
242 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
243 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
244 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
245 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
246 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
247 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
248 "WF1_TOP_CLK", "WF1_TOP_DATA";
249 drive-strength = <MTK_DRIVE_4mA>;
250 };
251 };
developer565bacb2021-09-28 21:26:32 +0800252};