blob: 0706d1819ad7f5af614ee6412ef233ea1b0e0642 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
developercd6a1382022-01-11 15:45:19 +08007 compatible = "mediatek,mt7986b-2500wan-spim-snand-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080053 phy-handle = <&phy5>;
developer565bacb2021-09-28 21:26:32 +080054 };
55
56 gmac1: mac@1 {
57 compatible = "mediatek,eth-mac";
58 reg = <1>;
59 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080060 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +080061 };
62
63 mdio: mdio-bus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
developerf0a1e452022-08-15 12:06:11 +080067 reset-gpios = <&pio 6 1>;
68 reset-delay-us = <600>;
69
developer565bacb2021-09-28 21:26:32 +080070 phy5: phy@5 {
developerf0a1e452022-08-15 12:06:11 +080071 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +080072 reg = <5>;
developer565bacb2021-09-28 21:26:32 +080073 };
74
75 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080076 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +080077 reg = <6>;
developer565bacb2021-09-28 21:26:32 +080078 };
79
80 switch@0 {
81 compatible = "mediatek,mt7531";
82 reg = <31>;
83 reset-gpios = <&pio 5 0>;
84
85 ports {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 port@0 {
90 reg = <0>;
91 label = "lan0";
92 };
93
94 port@1 {
95 reg = <1>;
96 label = "lan1";
97 };
98
99 port@2 {
100 reg = <2>;
101 label = "lan2";
102 };
103
104 port@3 {
105 reg = <3>;
106 label = "lan3";
107 };
108
109 port@4 {
110 reg = <4>;
111 label = "lan4";
112 };
113
114 port@5 {
115 reg = <5>;
116 label = "lan5";
117 phy-mode = "2500base-x";
118
119 fixed-link {
120 speed = <2500>;
121 full-duplex;
122 pause;
123 };
124 };
125
126 port@6 {
127 reg = <6>;
128 label = "cpu";
129 ethernet = <&gmac0>;
130 phy-mode = "2500base-x";
131
132 fixed-link {
133 speed = <2500>;
134 full-duplex;
135 pause;
136 };
137 };
138 };
139 };
140 };
141};
142
143&hnat {
144 mtketh-wan = "eth1";
145 mtketh-lan = "lan";
146 mtketh-max-gmac = <2>;
147 status = "okay";
148};
149
150&spi0 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&spi_flash_pins>;
153 cs-gpios = <0>, <0>;
154 status = "okay";
155
156 spi_nor@0 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "jedec,spi-nor";
160 reg = <0>;
161 spi-max-frequency = <20000000>;
162 spi-tx-buswidth = <4>;
163 spi-rx-buswidth = <4>;
164 };
165
166 spi_nand: spi_nand@1 {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 compatible = "spi-nand";
170 reg = <1>;
171 spi-max-frequency = <20000000>;
172 spi-tx-buswidth = <4>;
173 spi-rx-buswidth = <4>;
174 };
175};
176
177/* Warning: pins shared with &uart2 */
178&spi1 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&spic_pins>;
181 status = "okay";
182};
183
184&wbsys {
185 mediatek,mtd-eeprom = <&factory 0x0000>;
186 status = "okay";
developere138bcd2021-12-06 09:20:47 +0800187 pinctrl-names = "default", "dbdc";
188 pinctrl-0 = <&wf_2g_5g_pins>;
189 pinctrl-1 = <&wf_dbdc_pins>;
developer565bacb2021-09-28 21:26:32 +0800190};
191
192&pio {
193 spi_flash_pins: spi-flash-pins-33-to-38 {
194 mux {
195 function = "flash";
196 groups = "spi0", "spi0_wp_hold";
197 };
198 conf-pu {
199 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
200 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800201 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800202 };
203 conf-pd {
204 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
205 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800206 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800207 };
208
209 };
developere138bcd2021-12-06 09:20:47 +0800210
211 wf_2g_5g_pins: wf_2g_5g-pins {
212 mux {
213 function = "wifi";
214 groups = "wf_2g", "wf_5g";
215 };
216 conf {
217 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
218 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
219 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
220 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
221 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
222 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
223 "WF1_TOP_CLK", "WF1_TOP_DATA";
224 drive-strength = <MTK_DRIVE_4mA>;
225 };
226 };
227
228 wf_dbdc_pins: wf_dbdc-pins {
229 mux {
230 function = "wifi";
231 groups = "wf_dbdc";
232 };
233 conf {
234 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
235 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
236 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
237 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
238 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
239 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
240 "WF1_TOP_CLK", "WF1_TOP_DATA";
241 drive-strength = <MTK_DRIVE_4mA>;
242 };
243 };
developer565bacb2021-09-28 21:26:32 +0800244};