blob: 745606f16f1b032f6ab8a18e27f54ec67b723b53 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developera1c200a2022-03-04 20:10:00 +08005 compatible = "mediatek,mt7981-spim-snand-2500wan-gmac2-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer7e6086a2022-05-18 14:50:36 +080016 gpio-keys {
17 compatible = "gpio-keys";
18 reset {
19 label = "reset";
20 linux,code = <KEY_RESTART>;
21 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
22 };
23
24 wps {
25 label = "wps";
26 linux,code = <KEY_WPS_BUTTON>;
27 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
developer63866c92021-11-15 12:05:13 +080031 nmbm_spim_nand {
developer24455dd2021-10-28 10:55:41 +080032 compatible = "generic,nmbm";
33
34 #address-cells = <1>;
35 #size-cells = <1>;
36
developer63866c92021-11-15 12:05:13 +080037 lower-mtd-device = <&spi_nand>;
developer24455dd2021-10-28 10:55:41 +080038 forced-create;
developer24455dd2021-10-28 10:55:41 +080039
40 partitions {
41 compatible = "fixed-partitions";
42 #address-cells = <1>;
43 #size-cells = <1>;
44
45 partition@0 {
46 label = "BL2";
47 reg = <0x00000 0x0100000>;
48 read-only;
49 };
50
51 partition@100000 {
52 label = "u-boot-env";
53 reg = <0x0100000 0x0080000>;
54 };
55
developer63866c92021-11-15 12:05:13 +080056 partition@180000 {
developer24455dd2021-10-28 10:55:41 +080057 label = "Factory";
58 reg = <0x180000 0x0200000>;
59 };
60
61 partition@380000 {
62 label = "FIP";
63 reg = <0x380000 0x0200000>;
64 };
65
66 partition@580000 {
67 label = "ubi";
68 reg = <0x580000 0x4000000>;
69 };
70 };
71 };
72};
73
74&uart0 {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
89
90 fixed-link {
91 speed = <2500>;
92 full-duplex;
93 pause;
94 };
95 };
96
97 gmac1: mac@1 {
98 compatible = "mediatek,eth-mac";
99 reg = <1>;
100 phy-mode = "2500base-x";
101
102 fixed-link {
103 speed = <2500>;
104 full-duplex;
105 pause;
106 };
107 };
108
109 mdio: mdio-bus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
developer32805cd2022-01-06 17:08:06 +0800113 phy5: phy@5 {
114 compatible = "ethernet-phy-id67c9.de0a";
115 reg = <5>;
116 reset-gpios = <&pio 14 1>;
developer8c5a08b2022-05-06 09:10:38 +0800117 reset-assert-us = <600>;
developer32805cd2022-01-06 17:08:06 +0800118 reset-deassert-us = <20000>;
119 phy-mode = "2500base-x";
120 };
developer24455dd2021-10-28 10:55:41 +0800121
122 switch@0 {
123 compatible = "mediatek,mt7531";
124 reg = <31>;
125 reset-gpios = <&pio 39 0>;
developer24455dd2021-10-28 10:55:41 +0800126 ports {
127 #address-cells = <1>;
128 #size-cells = <0>;
129
130 port@0 {
131 reg = <0>;
132 label = "lan1";
133 };
134
135 port@1 {
136 reg = <1>;
137 label = "lan2";
138 };
139
140 port@2 {
141 reg = <2>;
142 label = "lan3";
143 };
144
145 port@3 {
146 reg = <3>;
147 label = "lan4";
148 };
149
150 port@6 {
151 reg = <6>;
152 label = "cpu";
153 ethernet = <&gmac0>;
154 phy-mode = "2500base-x";
155
156 fixed-link {
157 speed = <2500>;
158 full-duplex;
159 pause;
160 };
161 };
162 };
163 };
164 };
165};
166
167&hnat {
168 mtketh-wan = "eth1";
169 mtketh-lan = "lan";
170 mtketh-max-gmac = <2>;
171 status = "okay";
172};
173
developer63866c92021-11-15 12:05:13 +0800174&spi0 {
developer24455dd2021-10-28 10:55:41 +0800175 pinctrl-names = "default";
developer63866c92021-11-15 12:05:13 +0800176 pinctrl-0 = <&spi0_flash_pins>;
developer24455dd2021-10-28 10:55:41 +0800177 status = "okay";
developer63866c92021-11-15 12:05:13 +0800178 spi_nand: spi_nand@0 {
developer24455dd2021-10-28 10:55:41 +0800179 #address-cells = <1>;
180 #size-cells = <1>;
developer63866c92021-11-15 12:05:13 +0800181 compatible = "spi-nand";
182 reg = <0>;
183 spi-max-frequency = <52000000>;
184 spi-tx-buswidth = <4>;
185 spi-rx-buswidth = <4>;
developer24455dd2021-10-28 10:55:41 +0800186 };
187};
188
189&spi1 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&spic_pins>;
192 status = "disabled";
193};
194
195&pio {
196
developer63866c92021-11-15 12:05:13 +0800197 i2c_pins: i2c-pins-g0 {
198 mux {
199 function = "i2c";
200 groups = "i2c0_0";
201 };
202 };
203
204 pcm_pins: pcm-pins-g0 {
205 mux {
206 function = "pcm";
207 groups = "pcm";
208 };
209 };
210
211 pwm0_pin: pwm0-pin-g0 {
212 mux {
213 function = "pwm";
214 groups = "pwm0_0";
215 };
216 };
217
218 pwm1_pin: pwm1-pin-g0 {
219 mux {
220 function = "pwm";
221 groups = "pwm1_0";
222 };
223 };
224
225 pwm2_pin: pwm2-pin {
226 mux {
227 function = "pwm";
228 groups = "pwm2";
229 };
230 };
231
232 spi0_flash_pins: spi0-pins {
developer24455dd2021-10-28 10:55:41 +0800233 mux {
developer63866c92021-11-15 12:05:13 +0800234 function = "spi";
235 groups = "spi0", "spi0_wp_hold";
developer24455dd2021-10-28 10:55:41 +0800236 };
developer66b31fc2021-12-27 17:12:45 +0800237
238 conf-pu {
239 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
240 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800241 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800242 };
243
244 conf-pd {
245 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
246 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800247 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800248 };
developer24455dd2021-10-28 10:55:41 +0800249 };
250
251 spic_pins: spi1-pins {
252 mux {
253 function = "spi";
254 groups = "spi1_1";
255 };
256 };
developer63866c92021-11-15 12:05:13 +0800257
258 uart1_pins: uart1-pins-g1 {
259 mux {
260 function = "uart";
261 groups = "uart1_1";
262 };
263 };
264
265 uart2_pins: uart2-pins-g1 {
266 mux {
267 function = "uart";
268 groups = "uart2_1";
269 };
270 };
developer24455dd2021-10-28 10:55:41 +0800271};
272
273&xhci {
developer24455dd2021-10-28 10:55:41 +0800274 status = "okay";
275};