developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/module.h> |
| 4 | #include <linux/nvmem-consumer.h> |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 5 | #include <linux/of_address.h> |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 6 | #include <linux/of_platform.h> |
| 7 | #include <linux/phy.h> |
| 8 | |
| 9 | #define ANALOG_INTERNAL_OPERATION_MAX_US (20) |
| 10 | #define ZCAL_CTRL_MIN (0) |
| 11 | #define ZCAL_CTRL_MAX (63) |
| 12 | #define TXRESERVE_MIN (0) |
| 13 | #define TXRESERVE_MAX (7) |
| 14 | |
| 15 | |
| 16 | #define MTK_EXT_PAGE_ACCESS 0x1f |
| 17 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
| 18 | #define MTK_PHY_PAGE_EXTENDED 0x0001 |
| 19 | #define MTK_PHY_PAGE_EXTENDED_2 0x0002 |
| 20 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 21 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 22 | /* Registers on Page 3 */ |
| 23 | #define MTK_PHY_LPI_REG_14 (0x14) |
| 24 | #define MTK_PHY_LPI_WAKE_TIMER_1000 GENMASK(8, 0) |
| 25 | |
| 26 | #define MTK_PHY_LPI_REG_1c (0x1c) |
| 27 | #define MTK_PHY_SMI_DET_ON_THRESH GENMASK(13, 8) |
| 28 | /*******************************/ |
| 29 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 30 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 31 | #define MTK_PHY_ANARG_RG (0x10) |
| 32 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
| 33 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 34 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
| 35 | |
| 36 | /* Registers on MDIO_MMD_VEND1 */ |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 37 | enum { |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 38 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0, |
| 39 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 40 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 41 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_1TO0, |
| 42 | MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 43 | MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 44 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TON1, /* N means negative */ |
| 45 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 46 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 47 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_N1TO0, |
| 48 | MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 49 | MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 50 | MTK_PHY_TX_MLT3_END, |
| 51 | }; |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 52 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 53 | #define MTK_PHY_TXVLD_DA_RG (0x12) |
| 54 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
| 55 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
| 56 | |
| 57 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16) |
| 58 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
| 59 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
| 60 | |
| 61 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17) |
| 62 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
| 63 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
| 64 | |
| 65 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18) |
| 66 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
| 67 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
| 68 | |
| 69 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19) |
| 70 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
| 71 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
| 72 | |
| 73 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20) |
| 74 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
| 75 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
| 76 | |
| 77 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21) |
| 78 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
| 79 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
| 80 | |
| 81 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22) |
| 82 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
| 83 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
| 84 | |
| 85 | |
| 86 | #define MTK_PHY_RESERVE_RG_0 (0x27) |
| 87 | #define MTK_PHY_RESERVE_RG_1 (0x28) |
| 88 | |
| 89 | #define MTK_PHY_RG_ANA_TEST_POWERUP_TX (0x3b) |
| 90 | #define MTK_PHY_TANA_CAL_MODE (0xc1) |
| 91 | #define MTK_PHY_TANA_CAL_MODE_SHIFT (8) |
| 92 | |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 93 | #define MTK_PHY_RXADC_CTRL_RG7 (0xc6) |
| 94 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
| 95 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 96 | #define MTK_PHY_RXADC_CTRL_RG9 (0xc8) |
| 97 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
| 98 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
| 99 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
| 100 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
| 101 | |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 102 | #define MTK_PHY_LDO_OUTPUT_V (0xd7) |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 103 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 104 | #define MTK_PHY_RG_ANA_CAL_RG0 (0xdb) |
| 105 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
| 106 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
| 107 | #define MTK_PHY_RG_REXT_CALEN BIT(4) |
| 108 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
| 109 | |
| 110 | #define MTK_PHY_RG_ANA_CAL_RG1 (0xdc) |
| 111 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
| 112 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
| 113 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
| 114 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
| 115 | |
| 116 | #define MTK_PHY_RG_ANA_CAL_RG2 (0xdd) |
| 117 | #define MTK_PHY_RG_TXG_CALEN_A BIT(12) |
| 118 | #define MTK_PHY_RG_TXG_CALEN_B BIT(8) |
| 119 | #define MTK_PHY_RG_TXG_CALEN_C BIT(4) |
| 120 | #define MTK_PHY_RG_TXG_CALEN_D BIT(0) |
| 121 | |
| 122 | #define MTK_PHY_RG_ANA_CAL_RG5 (0xe0) |
| 123 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
| 124 | #define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0) |
| 125 | |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 126 | #define MTK_PHY_RG_TX_FILTER (0xfe) |
| 127 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 128 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 (0x120) |
| 129 | #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) |
| 130 | #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) |
| 131 | |
| 132 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 (0x122) |
| 133 | #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) |
| 134 | |
| 135 | #define MTK_PHY_RG_TESTMUX_ADC_CTRL (0x144) |
| 136 | #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) |
| 137 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 138 | #define MTK_PHY_RG_DEV1E_REG172 (0x172) |
| 139 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
| 140 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
| 141 | |
| 142 | #define MTK_PHY_RG_DEV1E_REG173 (0x173) |
| 143 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
| 144 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
| 145 | |
| 146 | #define MTK_PHY_RG_DEV1E_REG174 (0x174) |
| 147 | #define MTK_PHY_RSEL_TX_A_MASK GENMASK(14, 8) |
| 148 | #define MTK_PHY_RSEL_TX_B_MASK GENMASK(6, 0) |
| 149 | |
| 150 | #define MTK_PHY_RG_DEV1E_REG175 (0x175) |
| 151 | #define MTK_PHY_RSEL_TX_C_MASK GENMASK(14, 8) |
| 152 | #define MTK_PHY_RSEL_TX_D_MASK GENMASK(6, 0) |
| 153 | |
| 154 | #define MTK_PHY_RG_DEV1E_REG17A (0x17a) |
| 155 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
| 156 | |
| 157 | #define MTK_PHY_RG_DEV1E_REG17B (0x17b) |
| 158 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
| 159 | |
| 160 | #define MTK_PHY_RG_DEV1E_REG17C (0x17c) |
| 161 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
| 162 | |
| 163 | #define MTK_PHY_RG_DEV1E_REG17D (0x17d) |
| 164 | #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) |
| 165 | |
| 166 | #define MTK_PHY_RG_DEV1E_REG17E (0x17e) |
| 167 | #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) |
| 168 | |
| 169 | #define MTK_PHY_RG_DEV1E_REG17F (0x17f) |
| 170 | #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) |
| 171 | |
| 172 | #define MTK_PHY_RG_DEV1E_REG180 (0x180) |
| 173 | #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) |
| 174 | |
| 175 | #define MTK_PHY_RG_DEV1E_REG181 (0x181) |
| 176 | #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) |
| 177 | |
| 178 | #define MTK_PHY_RG_DEV1E_REG182 (0x182) |
| 179 | #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) |
| 180 | |
| 181 | #define MTK_PHY_RG_DEV1E_REG183 (0x183) |
| 182 | #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) |
| 183 | |
| 184 | #define MTK_PHY_RG_DEV1E_REG184 (0x180) |
| 185 | #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) |
| 186 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 187 | #define MTK_PHY_RG_DEV1E_REG19b (0x19b) |
| 188 | #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) |
| 189 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 190 | #define MTK_PHY_RG_LP_IIR2_K1_L (0x22a) |
| 191 | #define MTK_PHY_RG_LP_IIR2_K1_U (0x22b) |
| 192 | #define MTK_PHY_RG_LP_IIR2_K2_L (0x22c) |
| 193 | #define MTK_PHY_RG_LP_IIR2_K2_U (0x22d) |
| 194 | #define MTK_PHY_RG_LP_IIR2_K3_L (0x22e) |
| 195 | #define MTK_PHY_RG_LP_IIR2_K3_U (0x22f) |
| 196 | #define MTK_PHY_RG_LP_IIR2_K4_L (0x230) |
| 197 | #define MTK_PHY_RG_LP_IIR2_K4_U (0x231) |
| 198 | #define MTK_PHY_RG_LP_IIR2_K5_L (0x232) |
| 199 | #define MTK_PHY_RG_LP_IIR2_K5_U (0x233) |
| 200 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 201 | #define MTK_PHY_RG_DEV1E_REG234 (0x234) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 202 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
| 203 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 204 | #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 205 | |
| 206 | #define MTK_PHY_RG_LPF_CNT_VAL (0x235) |
| 207 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 208 | #define MTK_PHY_RG_DEV1E_REG238 (0x238) |
| 209 | #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) |
| 210 | #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) |
| 211 | |
| 212 | #define MTK_PHY_RG_DEV1E_REG239 (0x239) |
| 213 | #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) |
| 214 | #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) |
| 215 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 216 | #define MTK_PHY_RG_DEV1E_REG27C (0x27c) |
| 217 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
| 218 | #define MTK_PHY_RG_DEV1E_REG27D (0x27d) |
| 219 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 220 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 221 | #define MTK_PHY_RG_DEV1E_REG2C7 (0x2c7) |
| 222 | #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) |
| 223 | #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) |
| 224 | |
| 225 | #define MTK_PHY_RG_DEV1E_REG2D1 (0x2d1) |
| 226 | #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) |
| 227 | #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) |
| 228 | #define MTK_PHY_LPI_TR_READY BIT(9) |
| 229 | #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) |
| 230 | |
| 231 | #define MTK_PHY_RG_DEV1E_REG323 (0x323) |
| 232 | #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) |
| 233 | #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) |
| 234 | |
| 235 | #define MTK_PHY_RG_DEV1E_REG324 (0x324) |
| 236 | #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) |
| 237 | #define MTK_PHY_SMI_DET_MAX_EN BIT(8) |
| 238 | |
| 239 | #define MTK_PHY_RG_DEV1E_REG326 (0x326) |
| 240 | #define MTK_PHY_LPI_MODE_SD_ON BIT(0) |
| 241 | #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) |
| 242 | #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) |
| 243 | #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) |
| 244 | #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) |
| 245 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 246 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502) |
| 247 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503) |
| 248 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 249 | #define MTK_PHY_RG_DEV1E_REG53D (0x53d) |
| 250 | #define MTK_PHY_DA_TX_R50_A_NORMAL_MASK GENMASK(13, 8) |
| 251 | #define MTK_PHY_DA_TX_R50_A_TBT_MASK GENMASK(5, 0) |
| 252 | |
| 253 | #define MTK_PHY_RG_DEV1E_REG53E (0x53e) |
| 254 | #define MTK_PHY_DA_TX_R50_B_NORMAL_MASK GENMASK(13, 8) |
| 255 | #define MTK_PHY_DA_TX_R50_B_TBT_MASK GENMASK(5, 0) |
| 256 | |
| 257 | #define MTK_PHY_RG_DEV1E_REG53F (0x53f) |
| 258 | #define MTK_PHY_DA_TX_R50_C_NORMAL_MASK GENMASK(13, 8) |
| 259 | #define MTK_PHY_DA_TX_R50_C_TBT_MASK GENMASK(5, 0) |
| 260 | |
| 261 | #define MTK_PHY_RG_DEV1E_REG540 (0x540) |
| 262 | #define MTK_PHY_DA_TX_R50_D_NORMAL_MASK GENMASK(13, 8) |
| 263 | #define MTK_PHY_DA_TX_R50_D_TBT_MASK GENMASK(5, 0) |
| 264 | |
| 265 | |
| 266 | /* Registers on MDIO_MMD_VEND2 */ |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 267 | #define MTK_PHY_LED0_ON_CTRL (0x24) |
| 268 | #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) |
| 269 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 270 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 271 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 272 | #define MTK_PHY_LED0_ON_LINKDOWN BIT(3) |
| 273 | #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ |
| 274 | #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ |
| 275 | #define MTK_PHY_LED0_FORCE_ON BIT(6) |
| 276 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 277 | #define MTK_PHY_LED0_ENABLE BIT(15) |
| 278 | |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 279 | #define MTK_PHY_LED0_BLINK_CTRL (0x25) |
| 280 | #define MTK_PHY_LED0_1000TX BIT(0) |
| 281 | #define MTK_PHY_LED0_1000RX BIT(1) |
| 282 | #define MTK_PHY_LED0_100TX BIT(2) |
| 283 | #define MTK_PHY_LED0_100RX BIT(3) |
| 284 | #define MTK_PHY_LED0_10TX BIT(4) |
| 285 | #define MTK_PHY_LED0_10RX BIT(5) |
| 286 | #define MTK_PHY_LED0_COLLISION BIT(6) |
| 287 | #define MTK_PHY_LED0_RX_CRC_ERR BIT(7) |
| 288 | #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) |
| 289 | #define MTK_PHY_LED0_FORCE_BLINK BIT(9) |
| 290 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 291 | #define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100) |
| 292 | #define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8) |
| 293 | |
| 294 | #define MTK_PHY_RG_DEV1F_REG110 (0x110) |
| 295 | #define MTK_PHY_RG_TST_DMY2_MASK GENMASK(5, 0) |
| 296 | #define MTK_PHY_RG_TANA_RESERVE_MASK GENMASK(13, 8) |
| 297 | |
| 298 | #define MTK_PHY_RG_DEV1F_REG115 (0x115) |
| 299 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
| 300 | |
| 301 | /* |
| 302 | * These macro privides efuse parsing for internal phy. |
| 303 | */ |
| 304 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
| 305 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
| 306 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
| 307 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
| 308 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
| 309 | |
| 310 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
| 311 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
| 312 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
| 313 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
| 314 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
| 315 | |
| 316 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
| 317 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
| 318 | #define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0)) |
| 319 | #define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0)) |
| 320 | |
| 321 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
| 322 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
| 323 | |
| 324 | typedef enum { |
| 325 | PAIR_A, |
| 326 | PAIR_B, |
| 327 | PAIR_C, |
| 328 | PAIR_D, |
| 329 | } phy_cal_pair_t; |
| 330 | |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 331 | enum { |
| 332 | GPHY_PORT0, |
| 333 | GPHY_PORT1, |
| 334 | GPHY_PORT2, |
| 335 | GPHY_PORT3, |
| 336 | }; |
| 337 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 338 | const u8 mt798x_zcal_to_r50[64] = { |
| 339 | 7, 8, 9, 9, 10, 10, 11, 11, |
| 340 | 12, 13, 13, 14, 14, 15, 16, 16, |
| 341 | 17, 18, 18, 19, 20, 21, 21, 22, |
| 342 | 23, 24, 24, 25, 26, 27, 28, 29, |
| 343 | 30, 31, 32, 33, 34, 35, 36, 37, |
| 344 | 38, 40, 41, 42, 43, 45, 46, 48, |
| 345 | 49, 51, 52, 54, 55, 57, 59, 61, |
| 346 | 62, 63, 63, 63, 63, 63, 63, 63 |
| 347 | }; |
| 348 | |
| 349 | const char pair[4] = {'A', 'B', 'C', 'D'}; |
| 350 | |
| 351 | #define CAL_NO_PAIR(cal_item, cal_mode, ...) \ |
| 352 | cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__); |
| 353 | |
| 354 | #define CAL_PAIR_A_TO_A(cal_item, cal_mode, ...) \ |
| 355 | for(i=PAIR_A; i<=PAIR_A; i++) { \ |
| 356 | cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__, i);\ |
| 357 | if(cal_ret) break; \ |
| 358 | } |
| 359 | |
| 360 | #define CAL_PAIR_A_TO_D(cal_item, cal_mode, ...) \ |
| 361 | for(i=PAIR_A; i<=PAIR_D; i++) { \ |
| 362 | cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__, i);\ |
| 363 | if(cal_ret) break; \ |
| 364 | } |
| 365 | |
developer | c6e131e | 2021-12-08 12:36:24 +0800 | [diff] [blame] | 366 | #define SW_CAL(cal_item, cal_mode_get, pair_mode) \ |
| 367 | if(ret || (!ret && strcmp("sw", cal_mode_get) == 0)) { \ |
| 368 | CAL_##pair_mode(cal_item, sw) \ |
| 369 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 370 | |
| 371 | #define SW_EFUSE_CAL(cal_item, cal_mode_get, pair_mode,...) \ |
developer | c6e131e | 2021-12-08 12:36:24 +0800 | [diff] [blame] | 372 | if ((efs_valid && ret) || \ |
developer | 5736bab | 2022-08-10 17:32:07 +0800 | [diff] [blame] | 373 | (efs_valid && !ret && strcmp("efuse", cal_mode_get) == 0)) { \ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 374 | CAL_##pair_mode(cal_item, efuse, ##__VA_ARGS__) \ |
developer | c6e131e | 2021-12-08 12:36:24 +0800 | [diff] [blame] | 375 | } else if ((!efs_valid && ret) || \ |
| 376 | (!ret && strcmp("sw", cal_mode_get) == 0)) { \ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 377 | CAL_##pair_mode(cal_item, sw) \ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | #define EFUSE_CAL(cal_item, cal_mode_get, pair_mode, ...) \ |
| 381 | if ((efs_valid && ret) || \ |
developer | 5736bab | 2022-08-10 17:32:07 +0800 | [diff] [blame] | 382 | (efs_valid && !ret && strcmp("efuse", cal_mode_get) == 0)) {\ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 383 | CAL_##pair_mode(cal_item, efuse, ##__VA_ARGS__) \ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | #define CAL_FLOW(cal_item, cal_mode, cal_mode_get, pair_mode,...) \ |
| 387 | ret = of_property_read_string(phydev->mdio.dev.of_node, \ |
| 388 | #cal_item, &cal_mode_get); \ |
| 389 | cal_mode##_CAL(cal_item, cal_mode_get, pair_mode, ##__VA_ARGS__)\ |
developer | c6e131e | 2021-12-08 12:36:24 +0800 | [diff] [blame] | 390 | else { \ |
| 391 | dev_info(&phydev->mdio.dev, "%s cal mode %s%s," \ |
| 392 | " use default value," \ |
| 393 | " efs-valid: %s", \ |
| 394 | #cal_item, \ |
| 395 | ret? "" : cal_mode_get, \ |
| 396 | ret? "not specified" : " not supported", \ |
| 397 | efs_valid? "yes" : "no"); \ |
| 398 | } \ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 399 | if(cal_ret) { \ |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 400 | dev_err(&phydev->mdio.dev, "%s cal failed\n", #cal_item);\ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 401 | ret = -EIO; \ |
| 402 | goto out; \ |
| 403 | } |
| 404 | |
| 405 | static int mtk_gephy_read_page(struct phy_device *phydev) |
| 406 | { |
| 407 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
| 408 | } |
| 409 | |
| 410 | static int mtk_gephy_write_page(struct phy_device *phydev, int page) |
| 411 | { |
| 412 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); |
| 413 | } |
| 414 | |
| 415 | /* |
| 416 | * One calibration cycle consists of: |
| 417 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
| 418 | * until AD_CAL_COMP is ready to output calibration result. |
| 419 | * 2.Wait until DA_CAL_CLK is available. |
| 420 | * 3.Fetch AD_CAL_COMP_OUT. |
| 421 | */ |
| 422 | static int cal_cycle(struct phy_device *phydev, int devad, |
| 423 | u32 regnum, u16 mask, u16 cal_val) |
| 424 | { |
| 425 | unsigned long timeout; |
| 426 | int reg_val; |
| 427 | int ret; |
| 428 | |
| 429 | phy_modify_mmd(phydev, devad, regnum, |
| 430 | mask, cal_val); |
| 431 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17C, |
| 432 | MTK_PHY_DA_CALIN_FLAG); |
| 433 | |
| 434 | timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US); |
| 435 | do{ |
| 436 | reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17B); |
| 437 | } while(time_before(jiffies, timeout) && !(reg_val & BIT(0))); |
| 438 | |
| 439 | if(!(reg_val & BIT(0))) { |
| 440 | dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n"); |
| 441 | return -ETIMEDOUT; |
| 442 | } |
| 443 | |
| 444 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17C, |
| 445 | MTK_PHY_DA_CALIN_FLAG); |
| 446 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17A) >> |
| 447 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
| 448 | dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); |
| 449 | |
| 450 | return ret; |
| 451 | } |
| 452 | |
| 453 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
| 454 | { |
| 455 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 456 | MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); |
| 457 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG115, |
| 458 | MTK_PHY_RG_BG_RASEL_MASK, buf[1]); |
| 459 | |
| 460 | return 0; |
| 461 | } |
| 462 | |
| 463 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 464 | { |
| 465 | u16 rext_cal_val[2]; |
| 466 | |
| 467 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
| 468 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
| 469 | rext_fill_result(phydev, rext_cal_val); |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static int rext_cal_sw(struct phy_device *phydev) |
| 475 | { |
| 476 | u8 rg_zcal_ctrl_def; |
| 477 | u8 zcal_lower, zcal_upper, rg_zcal_ctrl; |
| 478 | u8 lower_ret, upper_ret; |
| 479 | u16 rext_cal_val[2]; |
| 480 | int ret; |
| 481 | |
| 482 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
| 483 | MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8); |
| 484 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 485 | MTK_PHY_RG_TXVOS_CALEN); |
| 486 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 487 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | MTK_PHY_RG_REXT_CALEN); |
| 488 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110, |
| 489 | MTK_PHY_RG_TST_DMY2_MASK, 0x1); |
| 490 | |
| 491 | rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5) & |
| 492 | MTK_PHY_RG_ZCAL_CTRL_MASK; |
| 493 | zcal_lower = ZCAL_CTRL_MIN; |
| 494 | zcal_upper = ZCAL_CTRL_MAX; |
| 495 | |
| 496 | dev_dbg(&phydev->mdio.dev, "Start REXT SW cal.\n"); |
| 497 | while((zcal_upper-zcal_lower) > 1) { |
| 498 | rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower+zcal_upper, 2); |
| 499 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 500 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 501 | if(ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 502 | zcal_upper = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 503 | upper_ret = ret; |
| 504 | } else if(ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 505 | zcal_lower = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 506 | lower_ret = ret; |
| 507 | } else |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 508 | goto restore; |
| 509 | } |
| 510 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 511 | if(zcal_lower == ZCAL_CTRL_MIN) { |
| 512 | ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 513 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower); |
| 514 | } else if(zcal_upper == ZCAL_CTRL_MAX) { |
| 515 | ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 516 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper); |
| 517 | } |
| 518 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 519 | goto restore; |
| 520 | |
| 521 | ret = upper_ret-lower_ret; |
| 522 | if (ret == 1) { |
| 523 | rext_cal_val[0] = zcal_upper; |
| 524 | rext_cal_val[1] = zcal_upper >> 3; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 525 | rext_fill_result(phydev, rext_cal_val); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 526 | dev_info(&phydev->mdio.dev, "REXT SW cal result: 0x%x\n", zcal_upper); |
| 527 | ret = 0; |
| 528 | } else |
| 529 | ret = -EINVAL; |
| 530 | |
| 531 | restore: |
| 532 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
| 533 | MTK_PHY_ANA_TEST_MODE_MASK); |
| 534 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 535 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | MTK_PHY_RG_REXT_CALEN); |
| 536 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110, |
| 537 | MTK_PHY_RG_TST_DMY2_MASK); |
| 538 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 539 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def); |
| 540 | |
| 541 | return ret; |
| 542 | } |
| 543 | |
| 544 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
| 545 | { |
| 546 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG172, |
| 547 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); |
| 548 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG172, |
| 549 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); |
| 550 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG173, |
| 551 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); |
| 552 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG173, |
| 553 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); |
| 554 | |
| 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 559 | { |
| 560 | u16 tx_offset_cal_val[4]; |
| 561 | |
| 562 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
| 563 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
| 564 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
| 565 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
| 566 | |
| 567 | tx_offset_fill_result(phydev, tx_offset_cal_val); |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
| 573 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 574 | int i; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 575 | int bias[16] = {0}; |
| 576 | switch(phydev->drv->phy_id) { |
| 577 | case 0x03a29461: |
| 578 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 579 | /* We add some calibration to efuse values |
| 580 | * due to board level influence. |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 581 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
| 582 | */ |
| 583 | int tmp[16] = { 7, 1, 4, 7, |
| 584 | 7, 1, 4, 7, |
| 585 | 7, 1, 4, 7, |
| 586 | 7, 1, 4, 7 }; |
| 587 | memcpy(bias, (const void *)tmp, sizeof(bias)); |
| 588 | break; |
| 589 | } |
| 590 | case 0x03a29481: |
| 591 | { |
| 592 | int tmp[16] = { 10, 6, 6, 10, |
| 593 | 10, 6, 6, 10, |
| 594 | 10, 6, 6, 10, |
| 595 | 10, 6, 6, 10 }; |
| 596 | memcpy(bias, (const void *)tmp, sizeof(bias)); |
| 597 | break; |
| 598 | } |
| 599 | default: |
| 600 | break; |
| 601 | } |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 602 | |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 603 | /* Prevent overflow */ |
| 604 | for (i = 0; i < 12; i++) { |
| 605 | if (buf[i>>2] + bias[i] > 63) { |
| 606 | buf[i>>2] = 63; |
| 607 | bias[i] = 0; |
| 608 | } else if (buf[i>>2] + bias[i] < 0) { |
| 609 | /* Bias caused by board design may change in the future. |
| 610 | * So check negative cases, too. |
| 611 | */ |
| 612 | buf[i>>2] = 0; |
| 613 | bias[i] = 0; |
| 614 | } |
| 615 | } |
| 616 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 617 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 618 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 619 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 620 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 621 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 622 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 623 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 624 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 625 | |
| 626 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 627 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 628 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 629 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 630 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 631 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 632 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 633 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 634 | |
| 635 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 636 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 637 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 638 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 639 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 640 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 641 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 642 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 643 | |
| 644 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 645 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 646 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 647 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 648 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 649 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 650 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 651 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 652 | |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 657 | { |
| 658 | u16 tx_amp_cal_val[4]; |
| 659 | |
| 660 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
| 661 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
| 662 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
| 663 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
| 664 | tx_amp_fill_result(phydev, tx_amp_cal_val); |
| 665 | |
| 666 | return 0; |
| 667 | } |
| 668 | |
| 669 | static int tx_r50_fill_result(struct phy_device *phydev, u16 *buf, |
| 670 | phy_cal_pair_t txg_calen_x) |
| 671 | { |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 672 | int bias[4] = {0}; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 673 | int i; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 674 | switch(phydev->drv->phy_id) { |
| 675 | case 0x03a29481: |
| 676 | { |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 677 | int tmp[16] = { -2, -2, -2, -2 }; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 678 | memcpy(bias, (const void *)tmp, sizeof(bias)); |
| 679 | break; |
| 680 | } |
| 681 | /* 0x03a29461 enters default case */ |
| 682 | default: |
| 683 | break; |
| 684 | } |
| 685 | |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 686 | for (i = 0; i < 4; i++) { |
| 687 | if (buf[i>>2] + bias[i] > 63) { |
| 688 | buf[i>>2] = 63; |
| 689 | bias[i] = 0; |
| 690 | } else if (buf[i>>2] + bias[i] < 0) { |
| 691 | buf[i>>2] = 0; |
| 692 | bias[i] = 0; |
| 693 | } |
| 694 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 695 | switch(txg_calen_x) { |
| 696 | case PAIR_A: |
| 697 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53D, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 698 | MTK_PHY_DA_TX_R50_A_NORMAL_MASK, (buf[0] + bias[0]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 699 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53D, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 700 | MTK_PHY_DA_TX_R50_A_TBT_MASK, (buf[0]) + bias[0]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 701 | break; |
| 702 | case PAIR_B: |
| 703 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53E, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 704 | MTK_PHY_DA_TX_R50_B_NORMAL_MASK, (buf[0] + bias[1])<< 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 705 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53E, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 706 | MTK_PHY_DA_TX_R50_B_TBT_MASK, (buf[0] + bias[1])); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 707 | break; |
| 708 | case PAIR_C: |
| 709 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53F, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 710 | MTK_PHY_DA_TX_R50_C_NORMAL_MASK, (buf[0] + bias[2])<< 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 711 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53F, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 712 | MTK_PHY_DA_TX_R50_C_TBT_MASK, (buf[0] + bias[2])); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 713 | break; |
| 714 | case PAIR_D: |
| 715 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG540, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 716 | MTK_PHY_DA_TX_R50_D_NORMAL_MASK, (buf[0] + bias[3])<< 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 717 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG540, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 718 | MTK_PHY_DA_TX_R50_D_TBT_MASK, (buf[0] + bias[3])); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 719 | break; |
| 720 | } |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
| 725 | phy_cal_pair_t txg_calen_x) |
| 726 | { |
| 727 | u16 tx_r50_cal_val[1]; |
| 728 | |
| 729 | switch(txg_calen_x) { |
| 730 | case PAIR_A: |
| 731 | tx_r50_cal_val[0] = EFS_DA_TX_R50_A(buf[1]); |
| 732 | break; |
| 733 | case PAIR_B: |
| 734 | tx_r50_cal_val[0] = EFS_DA_TX_R50_B(buf[1]); |
| 735 | break; |
| 736 | case PAIR_C: |
| 737 | tx_r50_cal_val[0] = EFS_DA_TX_R50_C(buf[2]); |
| 738 | break; |
| 739 | case PAIR_D: |
| 740 | tx_r50_cal_val[0] = EFS_DA_TX_R50_D(buf[2]); |
| 741 | break; |
| 742 | } |
| 743 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
| 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | static int tx_r50_cal_sw(struct phy_device *phydev, phy_cal_pair_t txg_calen_x) |
| 749 | { |
| 750 | u8 rg_zcal_ctrl_def; |
| 751 | u8 zcal_lower, zcal_upper, rg_zcal_ctrl; |
| 752 | u8 lower_ret, upper_ret; |
| 753 | u16 tx_r50_cal_val[1]; |
| 754 | int ret; |
| 755 | |
| 756 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
| 757 | MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8); |
| 758 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 759 | MTK_PHY_RG_TXVOS_CALEN); |
| 760 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 761 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN); |
| 762 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2, |
| 763 | BIT(txg_calen_x * 4)); |
| 764 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110, |
| 765 | MTK_PHY_RG_TST_DMY2_MASK, 0x1); |
| 766 | |
| 767 | rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5) & |
| 768 | MTK_PHY_RG_ZCAL_CTRL_MASK; |
| 769 | zcal_lower = ZCAL_CTRL_MIN; |
| 770 | zcal_upper = ZCAL_CTRL_MAX; |
| 771 | |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 772 | dev_dbg(&phydev->mdio.dev, "Start TX-R50 Pair%c SW cal.\n", pair[txg_calen_x]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 773 | while((zcal_upper-zcal_lower) > 1) { |
| 774 | rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower+zcal_upper, 2); |
| 775 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 776 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 777 | if(ret==1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 778 | zcal_upper = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 779 | upper_ret = ret; |
| 780 | } else if(ret==0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 781 | zcal_lower = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 782 | lower_ret = ret; |
| 783 | } else |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 784 | goto restore; |
| 785 | } |
| 786 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 787 | if(zcal_lower == ZCAL_CTRL_MIN) { |
| 788 | ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 789 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 790 | } else if(zcal_upper == ZCAL_CTRL_MAX) { |
| 791 | ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 792 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 793 | } |
| 794 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 795 | goto restore; |
| 796 | |
| 797 | ret = upper_ret-lower_ret; |
| 798 | if (ret == 1) { |
| 799 | tx_r50_cal_val[0] = mt798x_zcal_to_r50[zcal_upper]; |
| 800 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 801 | dev_info(&phydev->mdio.dev, "TX-R50 Pair%c SW cal result: 0x%x\n", |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 802 | pair[txg_calen_x], zcal_lower); |
| 803 | ret = 0; |
| 804 | } else |
| 805 | ret = -EINVAL; |
| 806 | |
| 807 | restore: |
| 808 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
| 809 | MTK_PHY_ANA_TEST_MODE_MASK); |
| 810 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 811 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN); |
| 812 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2, |
| 813 | BIT(txg_calen_x * 4)); |
| 814 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110, |
| 815 | MTK_PHY_RG_TST_DMY2_MASK); |
| 816 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 817 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def); |
| 818 | |
| 819 | return ret; |
| 820 | } |
| 821 | |
| 822 | static int tx_vcm_cal_sw(struct phy_device *phydev, phy_cal_pair_t rg_txreserve_x) |
| 823 | { |
| 824 | u8 lower_idx, upper_idx, txreserve_val; |
| 825 | u8 lower_ret, upper_ret; |
| 826 | int ret; |
| 827 | |
| 828 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 829 | MTK_PHY_RG_ANA_CALEN); |
| 830 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 831 | MTK_PHY_RG_CAL_CKINV); |
| 832 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 833 | MTK_PHY_RG_TXVOS_CALEN); |
| 834 | |
| 835 | switch(rg_txreserve_x) { |
| 836 | case PAIR_A: |
| 837 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17D, |
| 838 | MTK_PHY_DASN_DAC_IN0_A_MASK); |
| 839 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG181, |
| 840 | MTK_PHY_DASN_DAC_IN1_A_MASK); |
| 841 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 842 | MTK_PHY_RG_ZCALEN_A); |
| 843 | break; |
| 844 | case PAIR_B: |
| 845 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17E, |
| 846 | MTK_PHY_DASN_DAC_IN0_B_MASK); |
| 847 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG182, |
| 848 | MTK_PHY_DASN_DAC_IN1_B_MASK); |
| 849 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 850 | MTK_PHY_RG_ZCALEN_B); |
| 851 | break; |
| 852 | case PAIR_C: |
| 853 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17F, |
| 854 | MTK_PHY_DASN_DAC_IN0_C_MASK); |
| 855 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG183, |
| 856 | MTK_PHY_DASN_DAC_IN1_C_MASK); |
| 857 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 858 | MTK_PHY_RG_ZCALEN_C); |
| 859 | break; |
| 860 | case PAIR_D: |
| 861 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG180, |
| 862 | MTK_PHY_DASN_DAC_IN0_D_MASK); |
| 863 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG184, |
| 864 | MTK_PHY_DASN_DAC_IN1_D_MASK); |
| 865 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 866 | MTK_PHY_RG_ZCALEN_D); |
| 867 | break; |
| 868 | default: |
| 869 | ret = -EINVAL; |
| 870 | goto restore; |
| 871 | } |
| 872 | |
| 873 | lower_idx = TXRESERVE_MIN; |
| 874 | upper_idx = TXRESERVE_MAX; |
| 875 | |
| 876 | dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n"); |
| 877 | while((upper_idx-lower_idx) > 1) { |
| 878 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx+upper_idx, 2); |
| 879 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 880 | MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 881 | MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 882 | txreserve_val << 12 | txreserve_val << 8 | |
| 883 | txreserve_val << 4 | txreserve_val); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 884 | if(ret==1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 885 | upper_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 886 | upper_ret = ret; |
| 887 | } else if(ret==0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 888 | lower_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 889 | lower_ret = ret; |
| 890 | } else |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 891 | goto restore; |
| 892 | } |
| 893 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 894 | if(lower_idx == TXRESERVE_MIN) { |
| 895 | ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 896 | MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 897 | MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 898 | lower_idx << 12 | lower_idx << 8 | lower_idx << 4 | lower_idx); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 899 | } else if(upper_idx == TXRESERVE_MAX) { |
| 900 | ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 901 | MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 902 | MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 903 | upper_idx << 12 | upper_idx << 8 | upper_idx << 4 | upper_idx); |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 904 | } |
| 905 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 906 | goto restore; |
| 907 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 908 | /* We calibrate TX-VCM in different logic. Check upper index and then |
| 909 | * lower index. If this calibration is valid, apply lower index's result. |
| 910 | */ |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 911 | ret = upper_ret-lower_ret; |
| 912 | if (ret == 1) { |
| 913 | ret = 0; |
developer | b5c76d4 | 2022-08-18 15:45:33 +0800 | [diff] [blame] | 914 | /* Make sure we use upper_idx in our calibration system */ |
| 915 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 916 | MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 917 | MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 918 | upper_idx << 12 | upper_idx << 8 | upper_idx << 4 | upper_idx); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 919 | dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", upper_idx); |
| 920 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && lower_ret == 1) { |
| 921 | ret = 0; |
| 922 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 923 | MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 924 | MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 925 | lower_idx << 12 | lower_idx << 8 | lower_idx << 4 | lower_idx); |
| 926 | dev_warn(&phydev->mdio.dev, "TX-VCM SW cal result at low margin 0x%x\n", lower_idx); |
| 927 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && lower_ret == 0) { |
| 928 | ret = 0; |
| 929 | dev_warn(&phydev->mdio.dev, "TX-VCM SW cal result at high margin 0x%x\n", upper_idx); |
| 930 | } else |
| 931 | ret = -EINVAL; |
| 932 | |
| 933 | restore: |
| 934 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 935 | MTK_PHY_RG_ANA_CALEN); |
| 936 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 937 | MTK_PHY_RG_TXVOS_CALEN); |
| 938 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 939 | MTK_PHY_RG_ZCALEN_A); |
| 940 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 941 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | MTK_PHY_RG_ZCALEN_D); |
| 942 | |
| 943 | return ret; |
| 944 | } |
| 945 | |
| 946 | static void mtk_gephy_config_init(struct phy_device *phydev) |
| 947 | { |
| 948 | /* Disable EEE */ |
| 949 | phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); |
| 950 | |
| 951 | /* Enable HW auto downshift */ |
| 952 | phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); |
| 953 | |
| 954 | /* Increase SlvDPSready time */ |
| 955 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 956 | __phy_write(phydev, 0x10, 0xafae); |
| 957 | __phy_write(phydev, 0x12, 0x2f); |
| 958 | __phy_write(phydev, 0x10, 0x8fae); |
| 959 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 960 | |
| 961 | /* Adjust 100_mse_threshold */ |
| 962 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); |
| 963 | |
| 964 | /* Disable mcc */ |
| 965 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); |
| 966 | } |
| 967 | |
| 968 | static int mt7530_phy_config_init(struct phy_device *phydev) |
| 969 | { |
| 970 | mtk_gephy_config_init(phydev); |
| 971 | |
| 972 | /* Increase post_update_timer */ |
| 973 | phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static int mt7531_phy_config_init(struct phy_device *phydev) |
| 979 | { |
| 980 | if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) |
| 981 | return -EINVAL; |
| 982 | |
| 983 | mtk_gephy_config_init(phydev); |
| 984 | |
| 985 | /* PHY link down power saving enable */ |
| 986 | phy_set_bits(phydev, 0x17, BIT(4)); |
| 987 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); |
| 988 | |
| 989 | /* Set TX Pair delay selection */ |
| 990 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); |
| 991 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); |
| 992 | |
| 993 | return 0; |
| 994 | } |
| 995 | |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 996 | static inline void mt798x_phy_eee(struct phy_device *phydev) |
| 997 | { |
| 998 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 999 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, |
| 1000 | MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | |
| 1001 | MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, |
| 1002 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | |
| 1003 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); |
| 1004 | |
| 1005 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1006 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 1007 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 1008 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
| 1009 | |
| 1010 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1011 | MTK_PHY_RG_TESTMUX_ADC_CTRL, MTK_PHY_RG_TXEN_DIG_MASK); |
| 1012 | |
| 1013 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1014 | MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); |
| 1015 | |
| 1016 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1017 | MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); |
| 1018 | |
| 1019 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, |
| 1020 | MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | MTK_PHY_LPI_SLV_SEND_TX_EN, |
| 1021 | FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); |
| 1022 | |
| 1023 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, |
| 1024 | MTK_PHY_LPI_SEND_LOC_TIMER_MASK | MTK_PHY_LPI_TXPCS_LOC_RCV, |
| 1025 | FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); |
| 1026 | |
| 1027 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, |
| 1028 | MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, |
| 1029 | FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | |
| 1030 | FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); |
| 1031 | |
| 1032 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, |
| 1033 | MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 1034 | FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 0x33) | |
| 1035 | MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | |
| 1036 | MTK_PHY_LPI_VCO_EEE_STG0_EN); |
| 1037 | |
| 1038 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, |
| 1039 | MTK_PHY_EEE_WAKE_MAS_INT_DC | MTK_PHY_EEE_WAKE_SLV_INT_DC); |
| 1040 | |
| 1041 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, |
| 1042 | MTK_PHY_SMI_DETCNT_MAX_MASK, |
| 1043 | FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | |
| 1044 | MTK_PHY_SMI_DET_MAX_EN); |
| 1045 | |
| 1046 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, |
| 1047 | MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | |
| 1048 | MTK_PHY_TREC_UPDATE_ENAB_CLR | |
| 1049 | MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | |
| 1050 | MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); |
| 1051 | |
| 1052 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 1053 | /* Regsigdet_sel_1000 = 0 */ |
| 1054 | __phy_write(phydev, 0x11, 0xb); |
| 1055 | __phy_write(phydev, 0x12, 0x0); |
| 1056 | __phy_write(phydev, 0x10, 0x9690); |
| 1057 | |
| 1058 | /* REG_EEE_st2TrKf1000 = 3 */ |
| 1059 | __phy_write(phydev, 0x11, 0x114f); |
| 1060 | __phy_write(phydev, 0x12, 0x2); |
| 1061 | __phy_write(phydev, 0x10, 0x969a); |
| 1062 | |
| 1063 | /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ |
| 1064 | __phy_write(phydev, 0x11, 0x3028); |
| 1065 | __phy_write(phydev, 0x12, 0x0); |
| 1066 | __phy_write(phydev, 0x10, 0x969e); |
| 1067 | |
| 1068 | /* RegEEE_slv_wake_int_timer_tar = 8 */ |
| 1069 | __phy_write(phydev, 0x11, 0x5010); |
| 1070 | __phy_write(phydev, 0x12, 0x0); |
| 1071 | __phy_write(phydev, 0x10, 0x96a0); |
| 1072 | |
| 1073 | /* RegEEE_trfreeze_timer2 = 586 */ |
| 1074 | __phy_write(phydev, 0x11, 0x24a); |
| 1075 | __phy_write(phydev, 0x12, 0x0); |
| 1076 | __phy_write(phydev, 0x10, 0x96a8); |
| 1077 | |
| 1078 | /* RegEEE100Stg1_tar = 16 */ |
| 1079 | __phy_write(phydev, 0x11, 0x3210); |
| 1080 | __phy_write(phydev, 0x12, 0x0); |
| 1081 | __phy_write(phydev, 0x10, 0x96b8); |
| 1082 | |
| 1083 | /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ |
| 1084 | __phy_write(phydev, 0x11, 0x1463); |
| 1085 | __phy_write(phydev, 0x12, 0x0); |
| 1086 | __phy_write(phydev, 0x10, 0x96ca); |
| 1087 | |
| 1088 | /* DfeTailEnableVgaThresh1000 = 27 */ |
| 1089 | __phy_write(phydev, 0x11, 0x36); |
| 1090 | __phy_write(phydev, 0x12, 0x0); |
| 1091 | __phy_write(phydev, 0x10, 0x8f80); |
| 1092 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1093 | |
| 1094 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); |
| 1095 | __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000, |
| 1096 | FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000, 0x19c)); |
| 1097 | |
| 1098 | __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH, |
| 1099 | FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH, 0xc)); |
| 1100 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1101 | |
| 1102 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1103 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 1104 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 1105 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
| 1106 | } |
| 1107 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1108 | static inline void mt7981_phy_finetune(struct phy_device *phydev) |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 1109 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1110 | u32 i; |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 1111 | /* 100M eye finetune: |
| 1112 | * Keep middle level of TX MLT3 shapper as default. |
| 1113 | * Only change TX MLT3 overshoot level here. |
| 1114 | */ |
| 1115 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, 0x1ce); |
| 1116 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, 0x1c1); |
| 1117 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, 0x20f); |
| 1118 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, 0x202); |
| 1119 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, 0x3d0); |
| 1120 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, 0x3c0); |
| 1121 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, 0x13); |
| 1122 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, 0x5); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1123 | |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 1124 | /* TX-AMP finetune: |
| 1125 | * 100M +4, 1000M +6 to default value. |
| 1126 | * If efuse values aren't valid, TX-AMP uses the below values. |
| 1127 | */ |
| 1128 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 0x9824); |
| 1129 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 0x9026); |
| 1130 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 0x2624); |
| 1131 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 0x2426); |
| 1132 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 0x2624); |
| 1133 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 0x2426); |
| 1134 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 0x2624); |
| 1135 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 0x2426); |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1136 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1137 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 1138 | /* EnabRandUpdTrig = 1 */ |
| 1139 | __phy_write(phydev, 0x11, 0x2f00); |
| 1140 | __phy_write(phydev, 0x12, 0xe); |
| 1141 | __phy_write(phydev, 0x10, 0x8fb0); |
| 1142 | |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1143 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ |
| 1144 | __phy_write(phydev, 0x11, 0xc71); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1145 | __phy_write(phydev, 0x12, 0xc); |
| 1146 | __phy_write(phydev, 0x10, 0x8fae); |
| 1147 | |
| 1148 | /* NormMseLoThresh = 85 */ |
| 1149 | __phy_write(phydev, 0x11, 0x55a0); |
| 1150 | __phy_write(phydev, 0x12, 0x0); |
| 1151 | __phy_write(phydev, 0x10, 0x83aa); |
| 1152 | |
| 1153 | /* InhibitDisableDfeTail1000 = 1 */ |
| 1154 | __phy_write(phydev, 0x11, 0x2b); |
| 1155 | __phy_write(phydev, 0x12, 0x0); |
| 1156 | __phy_write(phydev, 0x10, 0x8f80); |
| 1157 | |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1158 | /* SSTrKp1000Slv = 5 */ |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1159 | __phy_write(phydev, 0x11, 0xbaef); |
| 1160 | __phy_write(phydev, 0x12, 0x2e); |
| 1161 | __phy_write(phydev, 0x10, 0x968c); |
| 1162 | |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1163 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 1164 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 1165 | */ |
| 1166 | __phy_write(phydev, 0x11, 0xd10a); |
| 1167 | __phy_write(phydev, 0x12, 0x34); |
| 1168 | __phy_write(phydev, 0x10, 0x8f82); |
| 1169 | |
| 1170 | /* TrFreeze = 0 */ |
| 1171 | __phy_write(phydev, 0x11, 0x0); |
| 1172 | __phy_write(phydev, 0x12, 0x0); |
| 1173 | __phy_write(phydev, 0x10, 0x9686); |
| 1174 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1175 | /* VcoSlicerThreshBitsHigh */ |
| 1176 | __phy_write(phydev, 0x11, 0x5555); |
| 1177 | __phy_write(phydev, 0x12, 0x55); |
| 1178 | __phy_write(phydev, 0x10, 0x8ec0); |
| 1179 | |
| 1180 | /* ResetSyncOffset = 6 */ |
| 1181 | __phy_write(phydev, 0x11, 0x600); |
| 1182 | __phy_write(phydev, 0x12, 0x0); |
| 1183 | __phy_write(phydev, 0x10, 0x8fc0); |
| 1184 | |
| 1185 | /* VgaDecRate = 1 */ |
| 1186 | __phy_write(phydev, 0x11, 0x4c2a); |
| 1187 | __phy_write(phydev, 0x12, 0x3e); |
| 1188 | __phy_write(phydev, 0x10, 0x8fa4); |
| 1189 | |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1190 | /* FfeUpdGainForce = 4 */ |
| 1191 | __phy_write(phydev, 0x11, 0x240); |
| 1192 | __phy_write(phydev, 0x12, 0x0); |
| 1193 | __phy_write(phydev, 0x10, 0x9680); |
| 1194 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1195 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1196 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1197 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1198 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 1199 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1200 | |
| 1201 | /* rg_tr_lpf_cnt_val = 512 */ |
| 1202 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 1203 | |
| 1204 | /* IIR2 related */ |
| 1205 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 1206 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 1207 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 1208 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 1209 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 1210 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 1211 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 1212 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 1213 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 1214 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 1215 | |
| 1216 | /* FFE peaking */ |
| 1217 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
| 1218 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
| 1219 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
| 1220 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
| 1221 | |
| 1222 | /* TX shape */ |
| 1223 | /* 10/100/1000 TX shaper is enabled by default */ |
| 1224 | for (i = 0x202; i < 0x230; i += 2) { |
| 1225 | if (i == 0x20c || i == 0x218 || i == 0x224) |
| 1226 | continue; |
| 1227 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219); |
| 1228 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i+1, 0x23); |
| 1229 | } |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1230 | |
| 1231 | /* Disable LDO pump */ |
| 1232 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 1233 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 1234 | |
| 1235 | /* Adjust LDO output voltage */ |
| 1236 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 1237 | |
| 1238 | mt798x_phy_eee(phydev); |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 1239 | } |
| 1240 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1241 | static inline void mt7988_phy_finetune(struct phy_device *phydev) |
| 1242 | { |
| 1243 | int i; |
| 1244 | u16 val[12] = {0x0187, 0x01cd, 0x01c8, 0x0182, |
| 1245 | 0x020d, 0x0206, 0x0384, 0x03d0, |
| 1246 | 0x03c6, 0x030a, 0x0011, 0x0005}; |
| 1247 | |
| 1248 | for(i=0; i<MTK_PHY_TX_MLT3_END; i++) { |
| 1249 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); |
| 1250 | } |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 1251 | |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 1252 | /* TCT finetune */ |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 1253 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 1254 | |
| 1255 | /* Disable TX power saving */ |
| 1256 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
developer | d1ea115 | 2022-10-13 18:24:48 +0800 | [diff] [blame] | 1257 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1258 | |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1259 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1260 | /* EnabRandUpdTrig = 1 */ |
| 1261 | __phy_write(phydev, 0x11, 0x2f00); |
| 1262 | __phy_write(phydev, 0x12, 0xe); |
| 1263 | __phy_write(phydev, 0x10, 0x8fb0); |
| 1264 | |
developer | cb32e04 | 2023-03-02 16:39:54 +0800 | [diff] [blame] | 1265 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1266 | __phy_write(phydev, 0x11, 0x671); |
| 1267 | __phy_write(phydev, 0x12, 0xc); |
| 1268 | __phy_write(phydev, 0x10, 0x8fae); |
| 1269 | |
| 1270 | /* NormMseLoThresh = 85 */ |
| 1271 | __phy_write(phydev, 0x11, 0x55a0); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1272 | __phy_write(phydev, 0x12, 0x0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1273 | __phy_write(phydev, 0x10, 0x83aa); |
| 1274 | |
| 1275 | /* InhibitDisableDfeTail1000 = 1 */ |
| 1276 | __phy_write(phydev, 0x11, 0x2b); |
| 1277 | __phy_write(phydev, 0x12, 0x0); |
| 1278 | __phy_write(phydev, 0x10, 0x8f80); |
| 1279 | |
| 1280 | /* SSTr related */ |
| 1281 | __phy_write(phydev, 0x11, 0xbaef); |
| 1282 | __phy_write(phydev, 0x12, 0x2e); |
| 1283 | __phy_write(phydev, 0x10, 0x968c); |
| 1284 | |
| 1285 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 1286 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 1287 | */ |
| 1288 | __phy_write(phydev, 0x11, 0xd10a); |
| 1289 | __phy_write(phydev, 0x12, 0x34); |
| 1290 | __phy_write(phydev, 0x10, 0x8f82); |
| 1291 | |
| 1292 | /* VcoSlicerThreshBitsHigh */ |
| 1293 | __phy_write(phydev, 0x11, 0x5555); |
| 1294 | __phy_write(phydev, 0x12, 0x55); |
| 1295 | __phy_write(phydev, 0x10, 0x8ec0); |
| 1296 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1297 | /* ResetSyncOffset = 5 */ |
| 1298 | __phy_write(phydev, 0x11, 0x500); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1299 | __phy_write(phydev, 0x12, 0x0); |
| 1300 | __phy_write(phydev, 0x10, 0x8fc0); |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1301 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1302 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1303 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); |
| 1304 | /* TxClkOffset = 2 */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1305 | __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1306 | FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1307 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1308 | |
| 1309 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
| 1310 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1311 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 1312 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1313 | |
| 1314 | /* rg_tr_lpf_cnt_val = 512 */ |
| 1315 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 1316 | |
| 1317 | /* IIR2 related */ |
| 1318 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 1319 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 1320 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 1321 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 1322 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 1323 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 1324 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 1325 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 1326 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 1327 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 1328 | |
| 1329 | /* FFE peaking */ |
| 1330 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
| 1331 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
| 1332 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
| 1333 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
| 1334 | |
| 1335 | /* TX shape */ |
| 1336 | /* 10/100/1000 TX shaper is enabled by default */ |
| 1337 | for (i = 0x202; i < 0x230; i += 2) { |
| 1338 | if (i == 0x20c || i == 0x218 || i == 0x224) |
| 1339 | continue; |
| 1340 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219); |
| 1341 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i+1, 0x23); |
| 1342 | } |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1343 | |
| 1344 | /* Disable LDO pump */ |
| 1345 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 1346 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 1347 | |
| 1348 | /* Adjust LDO output voltage */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1349 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 1350 | |
| 1351 | mt798x_phy_eee(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1352 | } |
| 1353 | |
| 1354 | static int mt798x_phy_calibration(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1355 | { |
| 1356 | const char *cal_mode_from_dts; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1357 | int i, ret; |
| 1358 | int cal_ret = 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1359 | u32 *buf; |
| 1360 | bool efs_valid = true; |
| 1361 | size_t len; |
| 1362 | struct nvmem_cell *cell; |
| 1363 | |
| 1364 | if (phydev->interface != PHY_INTERFACE_MODE_GMII) |
| 1365 | return -EINVAL; |
| 1366 | |
| 1367 | cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); |
| 1368 | if (IS_ERR(cell)) { |
| 1369 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1370 | return PTR_ERR(cell); |
| 1371 | return 0; |
| 1372 | } |
| 1373 | |
| 1374 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1375 | if (IS_ERR(buf)) |
| 1376 | return PTR_ERR(buf); |
| 1377 | nvmem_cell_put(cell); |
| 1378 | |
| 1379 | if(!buf[0] && !buf[1] && !buf[2] && !buf[3]) |
| 1380 | efs_valid = false; |
| 1381 | |
| 1382 | if (len < 4 * sizeof(u32)) { |
| 1383 | dev_err(&phydev->mdio.dev, "invalid calibration data\n"); |
| 1384 | ret = -EINVAL; |
| 1385 | goto out; |
| 1386 | } |
| 1387 | |
| 1388 | CAL_FLOW(rext, SW_EFUSE, cal_mode_from_dts, NO_PAIR, buf) |
| 1389 | CAL_FLOW(tx_offset, EFUSE, cal_mode_from_dts, NO_PAIR, buf) |
| 1390 | CAL_FLOW(tx_amp, EFUSE, cal_mode_from_dts, NO_PAIR, buf) |
| 1391 | CAL_FLOW(tx_r50, SW_EFUSE, cal_mode_from_dts, PAIR_A_TO_D, buf) |
| 1392 | CAL_FLOW(tx_vcm, SW, cal_mode_from_dts, PAIR_A_TO_A) |
developer | 6bd2371 | 2021-12-02 18:02:39 +0800 | [diff] [blame] | 1393 | ret = 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1394 | |
| 1395 | out: |
| 1396 | kfree(buf); |
| 1397 | return ret; |
| 1398 | } |
| 1399 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1400 | static int mt7981_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1401 | { |
| 1402 | mt7981_phy_finetune(phydev); |
| 1403 | |
| 1404 | return mt798x_phy_calibration(phydev); |
| 1405 | } |
| 1406 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1407 | static int mt7988_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1408 | { |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1409 | struct device_node *np; |
| 1410 | void __iomem *boottrap; |
| 1411 | u32 reg; |
| 1412 | int port; |
| 1413 | |
| 1414 | /* Setup LED polarity according to boottrap's polarity */ |
| 1415 | np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); |
| 1416 | if (!np) |
| 1417 | return -ENOENT; |
| 1418 | boottrap = of_iomap(np, 0); |
| 1419 | if (!boottrap) |
| 1420 | return -ENOMEM; |
| 1421 | reg = readl(boottrap); |
| 1422 | port = phydev->mdio.addr; |
| 1423 | if ((port == GPHY_PORT0 && reg & BIT(8)) || |
| 1424 | (port == GPHY_PORT1 && reg & BIT(9)) || |
| 1425 | (port == GPHY_PORT2 && reg & BIT(10)) || |
| 1426 | (port == GPHY_PORT3 && reg & BIT(11))) { |
| 1427 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1428 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 | |
| 1429 | MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000); |
| 1430 | } else { |
| 1431 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1432 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | |
| 1433 | MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 | |
| 1434 | MTK_PHY_LED0_ON_LINK1000); |
| 1435 | } |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 1436 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, |
| 1437 | MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | |
| 1438 | MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | |
| 1439 | MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1440 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1441 | mt7988_phy_finetune(phydev); |
| 1442 | |
| 1443 | return mt798x_phy_calibration(phydev); |
| 1444 | } |
| 1445 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1446 | static struct phy_driver mtk_gephy_driver[] = { |
| 1447 | #if 0 |
| 1448 | { |
| 1449 | PHY_ID_MATCH_EXACT(0x03a29412), |
| 1450 | .name = "MediaTek MT7530 PHY", |
| 1451 | .config_init = mt7530_phy_config_init, |
| 1452 | /* Interrupts are handled by the switch, not the PHY |
| 1453 | * itself. |
| 1454 | */ |
| 1455 | .config_intr = genphy_no_config_intr, |
| 1456 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1457 | .suspend = genphy_suspend, |
| 1458 | .resume = genphy_resume, |
| 1459 | .read_page = mtk_gephy_read_page, |
| 1460 | .write_page = mtk_gephy_write_page, |
| 1461 | }, |
| 1462 | { |
| 1463 | PHY_ID_MATCH_EXACT(0x03a29441), |
| 1464 | .name = "MediaTek MT7531 PHY", |
| 1465 | .config_init = mt7531_phy_config_init, |
| 1466 | /* Interrupts are handled by the switch, not the PHY |
| 1467 | * itself. |
| 1468 | */ |
| 1469 | .config_intr = genphy_no_config_intr, |
| 1470 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1471 | .suspend = genphy_suspend, |
| 1472 | .resume = genphy_resume, |
| 1473 | .read_page = mtk_gephy_read_page, |
| 1474 | .write_page = mtk_gephy_write_page, |
| 1475 | }, |
| 1476 | #endif |
| 1477 | { |
| 1478 | PHY_ID_MATCH_EXACT(0x03a29461), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1479 | .name = "MediaTek MT7981 PHY", |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1480 | .probe = mt7981_phy_probe, |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1481 | /* Interrupts are handled by the switch, not the PHY |
| 1482 | * itself. |
| 1483 | */ |
| 1484 | .config_intr = genphy_no_config_intr, |
| 1485 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1486 | .suspend = genphy_suspend, |
| 1487 | .resume = genphy_resume, |
| 1488 | .read_page = mtk_gephy_read_page, |
| 1489 | .write_page = mtk_gephy_write_page, |
| 1490 | }, |
| 1491 | { |
| 1492 | PHY_ID_MATCH_EXACT(0x03a29481), |
| 1493 | .name = "MediaTek MT7988 PHY", |
| 1494 | .probe = mt7988_phy_probe, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1495 | /* Interrupts are handled by the switch, not the PHY |
| 1496 | * itself. |
| 1497 | */ |
| 1498 | .config_intr = genphy_no_config_intr, |
| 1499 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1500 | .suspend = genphy_suspend, |
| 1501 | .resume = genphy_resume, |
| 1502 | .read_page = mtk_gephy_read_page, |
| 1503 | .write_page = mtk_gephy_write_page, |
| 1504 | }, |
| 1505 | }; |
| 1506 | |
| 1507 | module_phy_driver(mtk_gephy_driver); |
| 1508 | |
| 1509 | static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { |
| 1510 | { PHY_ID_MATCH_VENDOR(0x03a29400) }, |
| 1511 | { } |
| 1512 | }; |
| 1513 | |
| 1514 | MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); |
| 1515 | MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>"); |
| 1516 | MODULE_LICENSE("GPL"); |
| 1517 | |
| 1518 | MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); |