developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/module.h> |
| 4 | #include <linux/nvmem-consumer.h> |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 5 | #include <linux/of_address.h> |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 6 | #include <linux/of_platform.h> |
| 7 | #include <linux/phy.h> |
| 8 | |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 9 | #define MTK_GPHY_ID_MT7530 0x03a29412 |
| 10 | #define MTK_GPHY_ID_MT7531 0x03a29441 |
| 11 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
| 12 | #define MTK_GPHY_ID_MT7981 0x03a29461 |
| 13 | #define MTK_GPHY_ID_MT7988 0x03a29481 |
| 14 | #endif |
| 15 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 16 | #define MTK_EXT_PAGE_ACCESS 0x1f |
| 17 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
| 18 | #define MTK_PHY_PAGE_EXTENDED 0x0001 |
| 19 | #define MTK_PHY_PAGE_EXTENDED_2 0x0002 |
| 20 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 21 | /* Registers on Page 3 */ |
| 22 | #define MTK_PHY_LPI_REG_14 (0x14) |
| 23 | #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) |
| 24 | |
| 25 | #define MTK_PHY_LPI_REG_1c (0x1c) |
| 26 | #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) |
| 27 | /*******************************/ |
| 28 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 29 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
| 30 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
| 31 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 32 | #define ANALOG_INTERNAL_OPERATION_MAX_US (20) |
| 33 | #define ZCAL_CTRL_MIN (0) |
| 34 | #define ZCAL_CTRL_MAX (63) |
| 35 | #define TXRESERVE_MIN (0) |
| 36 | #define TXRESERVE_MAX (7) |
| 37 | |
| 38 | #define MTK_PHY_ANARG_RG (0x10) |
| 39 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
| 40 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 41 | /* Registers on MDIO_MMD_VEND1 */ |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 42 | enum { |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 43 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0, |
| 44 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 45 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 46 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_1TO0, |
| 47 | MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 48 | MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 49 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TON1, /* N means negative */ |
| 50 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 51 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 52 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_N1TO0, |
| 53 | MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 54 | MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 55 | MTK_PHY_TX_MLT3_END, |
| 56 | }; |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 57 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 58 | #define MTK_PHY_TXVLD_DA_RG (0x12) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 59 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
| 60 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
| 61 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 62 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 63 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
| 64 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
| 65 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 66 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 67 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
| 68 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
| 69 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 70 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 71 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
| 72 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
| 73 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 74 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 75 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
| 76 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
| 77 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 78 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 79 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
| 80 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
| 81 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 82 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 83 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
| 84 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
| 85 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 86 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 87 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
| 88 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
| 89 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 90 | #define MTK_PHY_TANA_CAL_MODE (0xc1) |
| 91 | #define MTK_PHY_TANA_CAL_MODE_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 92 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 93 | #define MTK_PHY_RXADC_CTRL_RG7 (0xc6) |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 94 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
| 95 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 96 | #define MTK_PHY_RXADC_CTRL_RG9 (0xc8) |
| 97 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
| 98 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
| 99 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
| 100 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 101 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 102 | #define MTK_PHY_LDO_OUTPUT_V (0xd7) |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 103 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 104 | #define MTK_PHY_RG_ANA_CAL_RG0 (0xdb) |
| 105 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
| 106 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
| 107 | #define MTK_PHY_RG_REXT_CALEN BIT(4) |
| 108 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 109 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 110 | #define MTK_PHY_RG_ANA_CAL_RG1 (0xdc) |
| 111 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
| 112 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
| 113 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
| 114 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 115 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 116 | #define MTK_PHY_RG_ANA_CAL_RG2 (0xdd) |
| 117 | #define MTK_PHY_RG_TXG_CALEN_A BIT(12) |
| 118 | #define MTK_PHY_RG_TXG_CALEN_B BIT(8) |
| 119 | #define MTK_PHY_RG_TXG_CALEN_C BIT(4) |
| 120 | #define MTK_PHY_RG_TXG_CALEN_D BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 121 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 122 | #define MTK_PHY_RG_ANA_CAL_RG5 (0xe0) |
| 123 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
| 124 | #define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 125 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 126 | #define MTK_PHY_RG_TX_FILTER (0xfe) |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 127 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 128 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 (0x120) |
| 129 | #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) |
| 130 | #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) |
| 131 | |
| 132 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 (0x122) |
| 133 | #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) |
| 134 | |
| 135 | #define MTK_PHY_RG_TESTMUX_ADC_CTRL (0x144) |
| 136 | #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) |
| 137 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 138 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B (0x172) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 139 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
| 140 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
| 141 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 142 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D (0x173) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 143 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
| 144 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
| 145 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 146 | #define MTK_PHY_RG_AD_CAL_COMP (0x17a) |
| 147 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 148 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 149 | #define MTK_PHY_RG_AD_CAL_CLK (0x17b) |
| 150 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 151 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 152 | #define MTK_PHY_RG_AD_CALIN (0x17c) |
| 153 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 154 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 155 | #define MTK_PHY_RG_DASN_DAC_IN0_A (0x17d) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 156 | #define MTK_PHY_FORCE_DASN_DAC_IN0_A BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 157 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 158 | #define MTK_PHY_RG_DASN_DAC_IN0_B (0x17e) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 159 | #define MTK_PHY_FORCE_DASN_DAC_IN0_B BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 160 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 161 | #define MTK_PHY_RG_DASN_DAC_IN0_C (0x17f) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 162 | #define MTK_PHY_FORCE_DASN_DAC_IN0_C BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 163 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 164 | #define MTK_PHY_RG_DASN_DAC_IN0_D (0x180) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 165 | #define MTK_PHY_FORCE_DASN_DAC_IN0_D BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 166 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 167 | #define MTK_PHY_RG_DASN_DAC_IN1_A (0x181) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 168 | #define MTK_PHY_FORCE_DASN_DAC_IN1_A BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 169 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 170 | #define MTK_PHY_RG_DASN_DAC_IN1_B (0x182) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 171 | #define MTK_PHY_FORCE_DASN_DAC_IN1_B BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 172 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 173 | #define MTK_PHY_RG_DASN_DAC_IN1_C (0x183) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 174 | #define MTK_PHY_FORCE_DASN_DAC_IN1_C BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 175 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 176 | #define MTK_PHY_RG_DASN_DAC_IN1_D (0x184) |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 177 | #define MTK_PHY_FORCE_DASN_DAC_IN1_D BIT(15) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 178 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 179 | #define MTK_PHY_RG_DEV1E_REG19b (0x19b) |
| 180 | #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) |
| 181 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 182 | #define MTK_PHY_RG_LP_IIR2_K1_L (0x22a) |
| 183 | #define MTK_PHY_RG_LP_IIR2_K1_U (0x22b) |
| 184 | #define MTK_PHY_RG_LP_IIR2_K2_L (0x22c) |
| 185 | #define MTK_PHY_RG_LP_IIR2_K2_U (0x22d) |
| 186 | #define MTK_PHY_RG_LP_IIR2_K3_L (0x22e) |
| 187 | #define MTK_PHY_RG_LP_IIR2_K3_U (0x22f) |
| 188 | #define MTK_PHY_RG_LP_IIR2_K4_L (0x230) |
| 189 | #define MTK_PHY_RG_LP_IIR2_K4_U (0x231) |
| 190 | #define MTK_PHY_RG_LP_IIR2_K5_L (0x232) |
| 191 | #define MTK_PHY_RG_LP_IIR2_K5_U (0x233) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 192 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 193 | #define MTK_PHY_RG_DEV1E_REG234 (0x234) |
| 194 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
| 195 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 196 | #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 197 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 198 | #define MTK_PHY_RG_LPF_CNT_VAL (0x235) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 199 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 200 | #define MTK_PHY_RG_DEV1E_REG238 (0x238) |
| 201 | #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) |
| 202 | #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) |
| 203 | |
| 204 | #define MTK_PHY_RG_DEV1E_REG239 (0x239) |
| 205 | #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) |
| 206 | #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) |
| 207 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 208 | #define MTK_PHY_RG_DEV1E_REG27C (0x27c) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 209 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 210 | #define MTK_PHY_RG_DEV1E_REG27D (0x27d) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 211 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 212 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 213 | #define MTK_PHY_RG_DEV1E_REG2C7 (0x2c7) |
| 214 | #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) |
| 215 | #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) |
| 216 | |
| 217 | #define MTK_PHY_RG_DEV1E_REG2D1 (0x2d1) |
| 218 | #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) |
| 219 | #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) |
| 220 | #define MTK_PHY_LPI_TR_READY BIT(9) |
| 221 | #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) |
| 222 | |
| 223 | #define MTK_PHY_RG_DEV1E_REG323 (0x323) |
| 224 | #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) |
| 225 | #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) |
| 226 | |
| 227 | #define MTK_PHY_RG_DEV1E_REG324 (0x324) |
| 228 | #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) |
| 229 | #define MTK_PHY_SMI_DET_MAX_EN BIT(8) |
| 230 | |
| 231 | #define MTK_PHY_RG_DEV1E_REG326 (0x326) |
| 232 | #define MTK_PHY_LPI_MODE_SD_ON BIT(0) |
| 233 | #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) |
| 234 | #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) |
| 235 | #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) |
| 236 | #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) |
| 237 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 238 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502) |
| 239 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 240 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 241 | #define MTK_PHY_DA_TX_R50_PAIR_A (0x53d) |
| 242 | #define MTK_PHY_DA_TX_R50_PAIR_B (0x53e) |
| 243 | #define MTK_PHY_DA_TX_R50_PAIR_C (0x53f) |
| 244 | #define MTK_PHY_DA_TX_R50_PAIR_D (0x540) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 245 | |
| 246 | /* Registers on MDIO_MMD_VEND2 */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 247 | #define MTK_PHY_LED0_ON_CTRL (0x24) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 248 | #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 249 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 250 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 251 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 252 | #define MTK_PHY_LED0_ON_LINKDOWN BIT(3) |
| 253 | #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ |
| 254 | #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ |
| 255 | #define MTK_PHY_LED0_FORCE_ON BIT(6) |
| 256 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 257 | #define MTK_PHY_LED0_ENABLE BIT(15) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 258 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 259 | #define MTK_PHY_LED0_BLINK_CTRL (0x25) |
| 260 | #define MTK_PHY_LED0_1000TX BIT(0) |
| 261 | #define MTK_PHY_LED0_1000RX BIT(1) |
| 262 | #define MTK_PHY_LED0_100TX BIT(2) |
| 263 | #define MTK_PHY_LED0_100RX BIT(3) |
| 264 | #define MTK_PHY_LED0_10TX BIT(4) |
| 265 | #define MTK_PHY_LED0_10RX BIT(5) |
| 266 | #define MTK_PHY_LED0_COLLISION BIT(6) |
| 267 | #define MTK_PHY_LED0_RX_CRC_ERR BIT(7) |
| 268 | #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) |
| 269 | #define MTK_PHY_LED0_FORCE_BLINK BIT(9) |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 270 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 271 | #define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 272 | #define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8) |
| 273 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 274 | #define MTK_PHY_RG_DASN_TXT_DMY2 (0x110) |
| 275 | #define MTK_PHY_TST_DMY2_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 276 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 277 | #define MTK_PHY_RG_BG_RASEL (0x115) |
| 278 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 279 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 280 | /* These macro privides efuse parsing for internal phy. */ |
| 281 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
| 282 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
| 283 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
| 284 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
| 285 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 286 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 287 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
| 288 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
| 289 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
| 290 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
| 291 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 292 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 293 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
| 294 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
| 295 | #define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0)) |
| 296 | #define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 297 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 298 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
| 299 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 300 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 301 | enum { |
| 302 | NO_PAIR, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 303 | PAIR_A, |
| 304 | PAIR_B, |
| 305 | PAIR_C, |
| 306 | PAIR_D, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 307 | }; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 308 | |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 309 | enum { |
| 310 | GPHY_PORT0, |
| 311 | GPHY_PORT1, |
| 312 | GPHY_PORT2, |
| 313 | GPHY_PORT3, |
| 314 | }; |
| 315 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 316 | enum calibration_mode { |
| 317 | EFUSE_K, |
| 318 | SW_K |
| 319 | }; |
| 320 | |
| 321 | enum CAL_ITEM { |
| 322 | REXT, |
| 323 | TX_OFFSET, |
| 324 | TX_AMP, |
| 325 | TX_R50, |
| 326 | TX_VCM |
| 327 | }; |
| 328 | |
| 329 | enum CAL_MODE { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 330 | EFUSE_M, |
| 331 | SW_M |
| 332 | }; |
| 333 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 334 | const u8 mt798x_zcal_to_r50[64] = { |
| 335 | 7, 8, 9, 9, 10, 10, 11, 11, |
| 336 | 12, 13, 13, 14, 14, 15, 16, 16, |
| 337 | 17, 18, 18, 19, 20, 21, 21, 22, |
| 338 | 23, 24, 24, 25, 26, 27, 28, 29, |
| 339 | 30, 31, 32, 33, 34, 35, 36, 37, |
| 340 | 38, 40, 41, 42, 43, 45, 46, 48, |
| 341 | 49, 51, 52, 54, 55, 57, 59, 61, |
| 342 | 62, 63, 63, 63, 63, 63, 63, 63 |
| 343 | }; |
| 344 | |
| 345 | const char pair[4] = {'A', 'B', 'C', 'D'}; |
| 346 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 347 | static int mtk_gephy_read_page(struct phy_device *phydev) |
| 348 | { |
| 349 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
| 350 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 351 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 352 | static int mtk_gephy_write_page(struct phy_device *phydev, int page) |
| 353 | { |
| 354 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); |
| 355 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 356 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 357 | static void mtk_gephy_config_init(struct phy_device *phydev) |
| 358 | { |
| 359 | /* Disable EEE */ |
| 360 | phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 361 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 362 | /* Enable HW auto downshift */ |
| 363 | phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 364 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 365 | /* Increase SlvDPSready time */ |
| 366 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 367 | __phy_write(phydev, 0x10, 0xafae); |
| 368 | __phy_write(phydev, 0x12, 0x2f); |
| 369 | __phy_write(phydev, 0x10, 0x8fae); |
| 370 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 371 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 372 | /* Adjust 100_mse_threshold */ |
| 373 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 374 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 375 | /* Disable mcc */ |
| 376 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); |
| 377 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 378 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 379 | static int mt7530_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 380 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 381 | mtk_gephy_config_init(phydev); |
| 382 | |
| 383 | /* Increase post_update_timer */ |
| 384 | phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); |
| 385 | |
| 386 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 387 | } |
| 388 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 389 | static int mt7531_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 390 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 391 | mtk_gephy_config_init(phydev); |
| 392 | |
| 393 | /* PHY link down power saving enable */ |
| 394 | phy_set_bits(phydev, 0x17, BIT(4)); |
| 395 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); |
| 396 | |
| 397 | /* Set TX Pair delay selection */ |
| 398 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); |
| 399 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); |
| 400 | |
| 401 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 402 | } |
| 403 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 404 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
| 405 | /* One calibration cycle consists of: |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 406 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
| 407 | * until AD_CAL_COMP is ready to output calibration result. |
| 408 | * 2.Wait until DA_CAL_CLK is available. |
| 409 | * 3.Fetch AD_CAL_COMP_OUT. |
| 410 | */ |
| 411 | static int cal_cycle(struct phy_device *phydev, int devad, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 412 | u32 regnum, u16 mask, u16 cal_val) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 413 | { |
| 414 | unsigned long timeout; |
| 415 | int reg_val; |
| 416 | int ret; |
| 417 | |
| 418 | phy_modify_mmd(phydev, devad, regnum, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 419 | mask, cal_val); |
| 420 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 421 | MTK_PHY_DA_CALIN_FLAG); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 422 | |
| 423 | timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 424 | do { |
| 425 | reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 426 | MTK_PHY_RG_AD_CAL_CLK); |
| 427 | } while (time_before(jiffies, timeout) && !(reg_val & BIT(0))); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 428 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 429 | if (!(reg_val & BIT(0))) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 430 | dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n"); |
| 431 | return -ETIMEDOUT; |
| 432 | } |
| 433 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 434 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 435 | MTK_PHY_DA_CALIN_FLAG); |
| 436 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> |
| 437 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 438 | dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); |
| 439 | |
| 440 | return ret; |
| 441 | } |
| 442 | |
| 443 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
| 444 | { |
| 445 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 446 | MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); |
| 447 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, |
| 448 | MTK_PHY_RG_BG_RASEL_MASK, buf[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 449 | |
| 450 | return 0; |
| 451 | } |
| 452 | |
| 453 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 454 | { |
| 455 | u16 rext_cal_val[2]; |
| 456 | |
| 457 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
| 458 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
| 459 | rext_fill_result(phydev, rext_cal_val); |
| 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 464 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
| 465 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 466 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 467 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 468 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 469 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 470 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 471 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 472 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 473 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 479 | { |
| 480 | u16 tx_offset_cal_val[4]; |
| 481 | |
| 482 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
| 483 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
| 484 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
| 485 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
| 486 | |
| 487 | tx_offset_fill_result(phydev, tx_offset_cal_val); |
| 488 | |
| 489 | return 0; |
| 490 | } |
| 491 | |
| 492 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
| 493 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 494 | int i; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 495 | int bias[16] = {0}; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 496 | const int vals_9461[16] = { 7, 1, 4, 7, |
| 497 | 7, 1, 4, 7, |
| 498 | 7, 1, 4, 7, |
| 499 | 7, 1, 4, 7 }; |
| 500 | const int vals_9481[16] = { 10, 6, 6, 10, |
| 501 | 10, 6, 6, 10, |
| 502 | 10, 6, 6, 10, |
| 503 | 10, 6, 6, 10 }; |
| 504 | |
| 505 | switch (phydev->drv->phy_id) { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 506 | case MTK_GPHY_ID_MT7981: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 507 | /* We add some calibration to efuse values |
| 508 | * due to board level influence. |
| 509 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
| 510 | */ |
| 511 | memcpy(bias, (const void *)vals_9461, sizeof(bias)); |
| 512 | for (i = 0; i <= 12; i += 4) { |
| 513 | if (likely(buf[i >> 2] + bias[i] >= 32)) { |
| 514 | bias[i] -= 13; |
| 515 | } else { |
| 516 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 517 | 0x5c, 0x7 << i, bias[i] << i); |
| 518 | bias[i + 1] += 13; |
| 519 | bias[i + 2] += 13; |
| 520 | bias[i + 3] += 13; |
| 521 | } |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 522 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 523 | break; |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 524 | case MTK_GPHY_ID_MT7988: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 525 | memcpy(bias, (const void *)vals_9481, sizeof(bias)); |
| 526 | break; |
| 527 | default: |
| 528 | break; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 529 | } |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 530 | |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 531 | /* Prevent overflow */ |
| 532 | for (i = 0; i < 12; i++) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 533 | if (buf[i >> 2] + bias[i] > 63) { |
| 534 | buf[i >> 2] = 63; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 535 | bias[i] = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 536 | } else if (buf[i >> 2] + bias[i] < 0) { |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 537 | /* Bias caused by board design may change in the future. |
| 538 | * So check negative cases, too. |
| 539 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 540 | buf[i >> 2] = 0; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 541 | bias[i] = 0; |
| 542 | } |
| 543 | } |
| 544 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 545 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 546 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 547 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 548 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 549 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 550 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 551 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 552 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 553 | |
| 554 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 555 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 556 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 557 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 558 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 559 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 560 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 561 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 562 | |
| 563 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 564 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 565 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 566 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 567 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 568 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 569 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 570 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 571 | |
| 572 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 573 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 574 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 575 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 576 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 577 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 578 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 579 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 580 | |
| 581 | return 0; |
| 582 | } |
| 583 | |
| 584 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 585 | { |
| 586 | u16 tx_amp_cal_val[4]; |
| 587 | |
| 588 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
| 589 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
| 590 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
| 591 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
| 592 | tx_amp_fill_result(phydev, tx_amp_cal_val); |
| 593 | |
| 594 | return 0; |
| 595 | } |
| 596 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 597 | static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, |
| 598 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 599 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 600 | int bias = 0; |
| 601 | u16 reg, val; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 602 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 603 | switch (phydev->drv->phy_id) { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 604 | case MTK_GPHY_ID_MT7988: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 605 | { |
| 606 | bias = -2; |
| 607 | break; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 608 | } |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 609 | /* MTK_GPHY_ID_MT7981 enters default case */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 610 | default: |
| 611 | break; |
| 612 | } |
| 613 | |
| 614 | val = clamp_val(bias + tx_r50_cal_val, 0, 63); |
| 615 | |
| 616 | switch (txg_calen_x) { |
| 617 | case PAIR_A: |
| 618 | reg = MTK_PHY_DA_TX_R50_PAIR_A; |
| 619 | break; |
| 620 | case PAIR_B: |
| 621 | reg = MTK_PHY_DA_TX_R50_PAIR_B; |
| 622 | break; |
| 623 | case PAIR_C: |
| 624 | reg = MTK_PHY_DA_TX_R50_PAIR_C; |
| 625 | break; |
| 626 | case PAIR_D: |
| 627 | reg = MTK_PHY_DA_TX_R50_PAIR_D; |
| 628 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 629 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 630 | |
| 631 | phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); |
| 632 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 637 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 638 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 639 | u16 tx_r50_cal_val; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 640 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 641 | switch (txg_calen_x) { |
| 642 | case PAIR_A: |
| 643 | tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); |
| 644 | break; |
| 645 | case PAIR_B: |
| 646 | tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); |
| 647 | break; |
| 648 | case PAIR_C: |
| 649 | tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); |
| 650 | break; |
| 651 | case PAIR_D: |
| 652 | tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); |
| 653 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 654 | } |
| 655 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
| 656 | |
| 657 | return 0; |
| 658 | } |
| 659 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 660 | static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 661 | { |
| 662 | u8 lower_idx, upper_idx, txreserve_val; |
| 663 | u8 lower_ret, upper_ret; |
| 664 | int ret; |
| 665 | |
| 666 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 667 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 668 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 669 | MTK_PHY_RG_CAL_CKINV); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 670 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 671 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 672 | |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 673 | /* Also clear bit[9:0] for MTK_PHY_RG_DASN_DAC_IN0/1_A/B/C/D */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 674 | switch (rg_txreserve_x) { |
| 675 | case PAIR_A: |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 676 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 677 | MTK_PHY_RG_DASN_DAC_IN0_A, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 678 | MTK_PHY_FORCE_DASN_DAC_IN0_A); |
| 679 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 680 | MTK_PHY_RG_DASN_DAC_IN1_A, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 681 | MTK_PHY_FORCE_DASN_DAC_IN1_A); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 682 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 683 | MTK_PHY_RG_ANA_CAL_RG0, |
| 684 | MTK_PHY_RG_ZCALEN_A); |
| 685 | break; |
| 686 | case PAIR_B: |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 687 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 688 | MTK_PHY_RG_DASN_DAC_IN0_B, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 689 | MTK_PHY_FORCE_DASN_DAC_IN0_B); |
| 690 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 691 | MTK_PHY_RG_DASN_DAC_IN1_B, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 692 | MTK_PHY_FORCE_DASN_DAC_IN1_B); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 693 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 694 | MTK_PHY_RG_ANA_CAL_RG1, |
| 695 | MTK_PHY_RG_ZCALEN_B); |
| 696 | break; |
| 697 | case PAIR_C: |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 698 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 699 | MTK_PHY_RG_DASN_DAC_IN0_C, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 700 | MTK_PHY_FORCE_DASN_DAC_IN0_C); |
| 701 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 702 | MTK_PHY_RG_DASN_DAC_IN1_C, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 703 | MTK_PHY_FORCE_DASN_DAC_IN1_C); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 704 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 705 | MTK_PHY_RG_ANA_CAL_RG1, |
| 706 | MTK_PHY_RG_ZCALEN_C); |
| 707 | break; |
| 708 | case PAIR_D: |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 709 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 710 | MTK_PHY_RG_DASN_DAC_IN0_D, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 711 | MTK_PHY_FORCE_DASN_DAC_IN0_D); |
| 712 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 713 | MTK_PHY_RG_DASN_DAC_IN1_D, |
developer | 76c9bcc | 2023-03-29 14:20:44 +0800 | [diff] [blame] | 714 | MTK_PHY_FORCE_DASN_DAC_IN1_D); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 715 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 716 | MTK_PHY_RG_ANA_CAL_RG1, |
| 717 | MTK_PHY_RG_ZCALEN_D); |
| 718 | break; |
| 719 | default: |
| 720 | ret = -EINVAL; |
| 721 | goto restore; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | lower_idx = TXRESERVE_MIN; |
| 725 | upper_idx = TXRESERVE_MAX; |
| 726 | |
| 727 | dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 728 | while ((upper_idx - lower_idx) > 1) { |
| 729 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 730 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 731 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 732 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 733 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 734 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 735 | txreserve_val << 12 | txreserve_val << 8 | |
| 736 | txreserve_val << 4 | txreserve_val); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 737 | if (ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 738 | upper_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 739 | upper_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 740 | } else if (ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 741 | lower_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 742 | lower_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 743 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 744 | goto restore; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 745 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 746 | } |
| 747 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 748 | if (lower_idx == TXRESERVE_MIN) { |
| 749 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 750 | MTK_PHY_RXADC_CTRL_RG9, |
| 751 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 752 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 753 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 754 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 755 | lower_idx << 12 | lower_idx << 8 | |
| 756 | lower_idx << 4 | lower_idx); |
| 757 | ret = lower_ret; |
| 758 | } else if (upper_idx == TXRESERVE_MAX) { |
| 759 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 760 | MTK_PHY_RXADC_CTRL_RG9, |
| 761 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 762 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 763 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 764 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 765 | upper_idx << 12 | upper_idx << 8 | |
| 766 | upper_idx << 4 | upper_idx); |
| 767 | ret = upper_ret; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 768 | } |
| 769 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 770 | goto restore; |
| 771 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 772 | /* We calibrate TX-VCM in different logic. Check upper index and then |
| 773 | * lower index. If this calibration is valid, apply lower index's result. |
| 774 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 775 | ret = upper_ret - lower_ret; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 776 | if (ret == 1) { |
| 777 | ret = 0; |
developer | b5c76d4 | 2022-08-18 15:45:33 +0800 | [diff] [blame] | 778 | /* Make sure we use upper_idx in our calibration system */ |
| 779 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 780 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 781 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 782 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 783 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 784 | upper_idx << 12 | upper_idx << 8 | |
| 785 | upper_idx << 4 | upper_idx); |
| 786 | dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", |
| 787 | upper_idx); |
| 788 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && |
| 789 | lower_ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 790 | ret = 0; |
| 791 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 792 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 793 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 794 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 795 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 796 | lower_idx << 12 | lower_idx << 8 | |
| 797 | lower_idx << 4 | lower_idx); |
| 798 | dev_warn(&phydev->mdio.dev, |
| 799 | "TX-VCM SW cal result at low margin 0x%x\n", |
| 800 | lower_idx); |
| 801 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && |
| 802 | lower_ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 803 | ret = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 804 | dev_warn(&phydev->mdio.dev, |
| 805 | "TX-VCM SW cal result at high margin 0x%x\n", |
| 806 | upper_idx); |
| 807 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 808 | ret = -EINVAL; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 809 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 810 | |
| 811 | restore: |
| 812 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 813 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 814 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 815 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 816 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 817 | MTK_PHY_RG_ZCALEN_A); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 818 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 819 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | |
| 820 | MTK_PHY_RG_ZCALEN_D); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 821 | |
| 822 | return ret; |
| 823 | } |
| 824 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 825 | static inline void mt798x_phy_common_finetune(struct phy_device *phydev) |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 826 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 827 | u32 i; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 828 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 829 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 830 | /* EnabRandUpdTrig = 1 */ |
| 831 | __phy_write(phydev, 0x11, 0x2f00); |
| 832 | __phy_write(phydev, 0x12, 0xe); |
| 833 | __phy_write(phydev, 0x10, 0x8fb0); |
| 834 | |
| 835 | /* NormMseLoThresh = 85 */ |
| 836 | __phy_write(phydev, 0x11, 0x55a0); |
| 837 | __phy_write(phydev, 0x12, 0x0); |
| 838 | __phy_write(phydev, 0x10, 0x83aa); |
| 839 | |
| 840 | /* InhibitDisableDfeTail1000 = 1 */ |
| 841 | __phy_write(phydev, 0x11, 0x2b); |
| 842 | __phy_write(phydev, 0x12, 0x0); |
| 843 | __phy_write(phydev, 0x10, 0x8f80); |
| 844 | |
| 845 | /* SSTrKp1000Slv = 5 */ |
| 846 | __phy_write(phydev, 0x11, 0xbaef); |
| 847 | __phy_write(phydev, 0x12, 0x2e); |
| 848 | __phy_write(phydev, 0x10, 0x968c); |
| 849 | |
| 850 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 851 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 852 | */ |
| 853 | __phy_write(phydev, 0x11, 0xd10a); |
| 854 | __phy_write(phydev, 0x12, 0x34); |
| 855 | __phy_write(phydev, 0x10, 0x8f82); |
| 856 | |
| 857 | /* VcoSlicerThreshBitsHigh */ |
| 858 | __phy_write(phydev, 0x11, 0x5555); |
| 859 | __phy_write(phydev, 0x12, 0x55); |
| 860 | __phy_write(phydev, 0x10, 0x8ec0); |
| 861 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 862 | |
| 863 | /* rg_tr_lpf_cnt_val = 512 */ |
| 864 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 865 | |
| 866 | /* IIR2 related */ |
| 867 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 868 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 869 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 870 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 871 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 872 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 873 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 874 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 875 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 876 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 877 | |
| 878 | /* FFE peaking */ |
| 879 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
| 880 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
| 881 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
| 882 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
| 883 | |
| 884 | /* TX shape */ |
| 885 | /* 10/100/1000 TX shaper is enabled by default */ |
| 886 | for (i = 0x202; i < 0x230; i += 2) { |
| 887 | if (i == 0x20c || i == 0x218 || i == 0x224) |
| 888 | continue; |
| 889 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219); |
| 890 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23); |
| 891 | } |
| 892 | |
| 893 | /* Disable LDO pump */ |
| 894 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 895 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 896 | /* Adjust LDO output voltage */ |
| 897 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
| 898 | } |
| 899 | |
| 900 | static inline void mt7981_phy_finetune(struct phy_device *phydev) |
| 901 | { |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 902 | /* 100M eye finetune: |
| 903 | * Keep middle level of TX MLT3 shapper as default. |
| 904 | * Only change TX MLT3 overshoot level here. |
| 905 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 906 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 907 | 0x1ce); |
| 908 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 909 | 0x1c1); |
| 910 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 911 | 0x20f); |
| 912 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 913 | 0x202); |
| 914 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 915 | 0x3d0); |
| 916 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 917 | 0x3c0); |
| 918 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 919 | 0x13); |
| 920 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 921 | 0x5); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 922 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 923 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 924 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ |
| 925 | __phy_write(phydev, 0x11, 0xc71); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 926 | __phy_write(phydev, 0x12, 0xc); |
| 927 | __phy_write(phydev, 0x10, 0x8fae); |
| 928 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 929 | /* TrFreeze = 0 */ |
| 930 | __phy_write(phydev, 0x11, 0x0); |
| 931 | __phy_write(phydev, 0x12, 0x0); |
| 932 | __phy_write(phydev, 0x10, 0x9686); |
| 933 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 934 | /* ResetSyncOffset = 6 */ |
| 935 | __phy_write(phydev, 0x11, 0x600); |
| 936 | __phy_write(phydev, 0x12, 0x0); |
| 937 | __phy_write(phydev, 0x10, 0x8fc0); |
| 938 | |
| 939 | /* VgaDecRate = 1 */ |
| 940 | __phy_write(phydev, 0x11, 0x4c2a); |
| 941 | __phy_write(phydev, 0x12, 0x3e); |
| 942 | __phy_write(phydev, 0x10, 0x8fa4); |
| 943 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 944 | /* FfeUpdGainForce = 4 */ |
| 945 | __phy_write(phydev, 0x11, 0x240); |
| 946 | __phy_write(phydev, 0x12, 0x0); |
| 947 | __phy_write(phydev, 0x10, 0x9680); |
| 948 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 949 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 950 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 951 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 952 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 953 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 954 | } |
| 955 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 956 | static inline void mt7988_phy_finetune(struct phy_device *phydev) |
| 957 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 958 | u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, |
| 959 | 0x020d, 0x0206, 0x0384, 0x03d0, |
| 960 | 0x03c6, 0x030a, 0x0011, 0x0005 }; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 961 | int i; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 962 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 963 | for (i = 0; i < MTK_PHY_TX_MLT3_END; i++) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 964 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 965 | |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 966 | /* TCT finetune */ |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 967 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 968 | |
| 969 | /* Disable TX power saving */ |
| 970 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 971 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 972 | |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 973 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 974 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 975 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 976 | __phy_write(phydev, 0x11, 0x671); |
| 977 | __phy_write(phydev, 0x12, 0xc); |
| 978 | __phy_write(phydev, 0x10, 0x8fae); |
| 979 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 980 | /* ResetSyncOffset = 5 */ |
| 981 | __phy_write(phydev, 0x11, 0x500); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 982 | __phy_write(phydev, 0x12, 0x0); |
| 983 | __phy_write(phydev, 0x10, 0x8fc0); |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 984 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 985 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 986 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); |
| 987 | /* TxClkOffset = 2 */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 988 | __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 989 | FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 990 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 991 | |
| 992 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
| 993 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 994 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 995 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 996 | } |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 997 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 998 | static inline void mt798x_phy_eee(struct phy_device *phydev) |
| 999 | { |
| 1000 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1001 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, |
| 1002 | MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | |
| 1003 | MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, |
| 1004 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | |
| 1005 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); |
| 1006 | |
| 1007 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1008 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 1009 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 1010 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
| 1011 | |
| 1012 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1013 | MTK_PHY_RG_TESTMUX_ADC_CTRL, MTK_PHY_RG_TXEN_DIG_MASK); |
| 1014 | |
| 1015 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1016 | MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); |
| 1017 | |
| 1018 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 1019 | MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); |
| 1020 | |
| 1021 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, |
| 1022 | MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | MTK_PHY_LPI_SLV_SEND_TX_EN, |
| 1023 | FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); |
| 1024 | |
| 1025 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, |
| 1026 | MTK_PHY_LPI_SEND_LOC_TIMER_MASK | MTK_PHY_LPI_TXPCS_LOC_RCV, |
| 1027 | FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); |
| 1028 | |
| 1029 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, |
| 1030 | MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, |
| 1031 | FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | |
| 1032 | FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); |
| 1033 | |
| 1034 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, |
| 1035 | MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 1036 | FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 0x33) | |
| 1037 | MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | |
| 1038 | MTK_PHY_LPI_VCO_EEE_STG0_EN); |
| 1039 | |
| 1040 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, |
| 1041 | MTK_PHY_EEE_WAKE_MAS_INT_DC | MTK_PHY_EEE_WAKE_SLV_INT_DC); |
| 1042 | |
| 1043 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, |
| 1044 | MTK_PHY_SMI_DETCNT_MAX_MASK, |
| 1045 | FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | |
| 1046 | MTK_PHY_SMI_DET_MAX_EN); |
| 1047 | |
| 1048 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, |
| 1049 | MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | |
| 1050 | MTK_PHY_TREC_UPDATE_ENAB_CLR | |
| 1051 | MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | |
| 1052 | MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); |
| 1053 | |
| 1054 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 1055 | /* Regsigdet_sel_1000 = 0 */ |
| 1056 | __phy_write(phydev, 0x11, 0xb); |
| 1057 | __phy_write(phydev, 0x12, 0x0); |
| 1058 | __phy_write(phydev, 0x10, 0x9690); |
| 1059 | |
| 1060 | /* REG_EEE_st2TrKf1000 = 3 */ |
| 1061 | __phy_write(phydev, 0x11, 0x114f); |
| 1062 | __phy_write(phydev, 0x12, 0x2); |
| 1063 | __phy_write(phydev, 0x10, 0x969a); |
| 1064 | |
| 1065 | /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ |
| 1066 | __phy_write(phydev, 0x11, 0x3028); |
| 1067 | __phy_write(phydev, 0x12, 0x0); |
| 1068 | __phy_write(phydev, 0x10, 0x969e); |
| 1069 | |
| 1070 | /* RegEEE_slv_wake_int_timer_tar = 8 */ |
| 1071 | __phy_write(phydev, 0x11, 0x5010); |
| 1072 | __phy_write(phydev, 0x12, 0x0); |
| 1073 | __phy_write(phydev, 0x10, 0x96a0); |
| 1074 | |
| 1075 | /* RegEEE_trfreeze_timer2 = 586 */ |
| 1076 | __phy_write(phydev, 0x11, 0x24a); |
| 1077 | __phy_write(phydev, 0x12, 0x0); |
| 1078 | __phy_write(phydev, 0x10, 0x96a8); |
| 1079 | |
| 1080 | /* RegEEE100Stg1_tar = 16 */ |
| 1081 | __phy_write(phydev, 0x11, 0x3210); |
| 1082 | __phy_write(phydev, 0x12, 0x0); |
| 1083 | __phy_write(phydev, 0x10, 0x96b8); |
| 1084 | |
| 1085 | /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ |
| 1086 | __phy_write(phydev, 0x11, 0x1463); |
| 1087 | __phy_write(phydev, 0x12, 0x0); |
| 1088 | __phy_write(phydev, 0x10, 0x96ca); |
| 1089 | |
| 1090 | /* DfeTailEnableVgaThresh1000 = 27 */ |
| 1091 | __phy_write(phydev, 0x11, 0x36); |
| 1092 | __phy_write(phydev, 0x12, 0x0); |
| 1093 | __phy_write(phydev, 0x10, 0x8f80); |
| 1094 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1095 | |
| 1096 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); |
| 1097 | __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, |
| 1098 | FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); |
| 1099 | |
| 1100 | __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, |
| 1101 | FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); |
| 1102 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1103 | |
| 1104 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1105 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 1106 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 1107 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
| 1108 | } |
| 1109 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1110 | static inline int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1111 | u8 start_pair, u8 end_pair) |
| 1112 | { |
| 1113 | u8 pair_n; |
| 1114 | int ret; |
| 1115 | |
| 1116 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1117 | /* TX_OFFSET & TX_AMP have no SW calibration. */ |
| 1118 | switch (cal_item) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1119 | case TX_VCM: |
| 1120 | ret = tx_vcm_cal_sw(phydev, pair_n); |
| 1121 | break; |
| 1122 | default: |
| 1123 | return -EINVAL; |
| 1124 | } |
| 1125 | if (ret) |
| 1126 | return ret; |
| 1127 | } |
| 1128 | return 0; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1129 | } |
| 1130 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1131 | static inline int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1132 | u8 start_pair, u8 end_pair, u32 *buf) |
| 1133 | { |
| 1134 | u8 pair_n; |
| 1135 | int ret; |
| 1136 | |
| 1137 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1138 | /* TX_VCM has no efuse calibration. */ |
| 1139 | switch (cal_item) { |
| 1140 | case REXT: |
| 1141 | ret = rext_cal_efuse(phydev, buf); |
| 1142 | break; |
| 1143 | case TX_OFFSET: |
| 1144 | ret = tx_offset_cal_efuse(phydev, buf); |
| 1145 | break; |
| 1146 | case TX_AMP: |
| 1147 | ret = tx_amp_cal_efuse(phydev, buf); |
| 1148 | break; |
| 1149 | case TX_R50: |
| 1150 | ret = tx_r50_cal_efuse(phydev, buf, pair_n); |
| 1151 | break; |
| 1152 | default: |
| 1153 | return -EINVAL; |
| 1154 | } |
| 1155 | if (ret) |
| 1156 | return ret; |
| 1157 | } |
| 1158 | |
| 1159 | return 0; |
| 1160 | } |
| 1161 | |
| 1162 | static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1163 | enum CAL_MODE cal_mode, u8 start_pair, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1164 | u8 end_pair, u32 *buf) |
| 1165 | { |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1166 | int ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1167 | char cal_prop[5][20] = { "mediatek,rext", "mediatek,tx_offset", |
| 1168 | "mediatek,tx_amp", "mediatek,tx_r50", |
| 1169 | "mediatek,tx_vcm" }; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1170 | |
| 1171 | switch (cal_mode) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1172 | case EFUSE_M: |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1173 | ret = cal_efuse(phydev, cal_item, start_pair, |
| 1174 | end_pair, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1175 | break; |
| 1176 | case SW_M: |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1177 | ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1178 | break; |
| 1179 | default: |
| 1180 | return -EINVAL; |
| 1181 | } |
| 1182 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1183 | if (ret) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1184 | dev_err(&phydev->mdio.dev, "[%s]cal failed\n", cal_prop[cal_item]); |
| 1185 | return -EIO; |
| 1186 | } |
| 1187 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1188 | return 0; |
| 1189 | } |
| 1190 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1191 | static int mt798x_phy_calibration(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1192 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1193 | int ret = 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1194 | u32 *buf; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1195 | size_t len; |
| 1196 | struct nvmem_cell *cell; |
| 1197 | |
| 1198 | if (phydev->interface != PHY_INTERFACE_MODE_GMII) |
| 1199 | return -EINVAL; |
| 1200 | |
| 1201 | cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); |
| 1202 | if (IS_ERR(cell)) { |
| 1203 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1204 | return PTR_ERR(cell); |
| 1205 | return 0; |
| 1206 | } |
| 1207 | |
| 1208 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1209 | if (IS_ERR(buf)) |
| 1210 | return PTR_ERR(buf); |
| 1211 | nvmem_cell_put(cell); |
| 1212 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1213 | if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { |
| 1214 | dev_err(&phydev->mdio.dev, "invalid efuse data\n"); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1215 | ret = -EINVAL; |
| 1216 | goto out; |
| 1217 | } |
| 1218 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1219 | ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1220 | if (ret) |
| 1221 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1222 | ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1223 | if (ret) |
| 1224 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1225 | ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1226 | if (ret) |
| 1227 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1228 | ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1229 | if (ret) |
| 1230 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1231 | ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1232 | if (ret) |
| 1233 | goto out; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1234 | |
| 1235 | out: |
| 1236 | kfree(buf); |
| 1237 | return ret; |
| 1238 | } |
| 1239 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1240 | static int mt7981_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1241 | { |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 1242 | mt798x_phy_common_finetune(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1243 | mt7981_phy_finetune(phydev); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1244 | mt798x_phy_eee(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1245 | |
| 1246 | return mt798x_phy_calibration(phydev); |
| 1247 | } |
| 1248 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1249 | static int mt7988_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1250 | { |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 1251 | mt798x_phy_common_finetune(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1252 | mt7988_phy_finetune(phydev); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1253 | mt798x_phy_eee(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1254 | |
| 1255 | return mt798x_phy_calibration(phydev); |
| 1256 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1257 | #endif |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1258 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1259 | static struct phy_driver mtk_gephy_driver[] = { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1260 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1261 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1262 | .name = "MediaTek MT7530 PHY", |
| 1263 | .config_init = mt7530_phy_config_init, |
| 1264 | /* Interrupts are handled by the switch, not the PHY |
| 1265 | * itself. |
| 1266 | */ |
| 1267 | .config_intr = genphy_no_config_intr, |
| 1268 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1269 | .suspend = genphy_suspend, |
| 1270 | .resume = genphy_resume, |
| 1271 | .read_page = mtk_gephy_read_page, |
| 1272 | .write_page = mtk_gephy_write_page, |
| 1273 | }, |
| 1274 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1275 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1276 | .name = "MediaTek MT7531 PHY", |
| 1277 | .config_init = mt7531_phy_config_init, |
| 1278 | /* Interrupts are handled by the switch, not the PHY |
| 1279 | * itself. |
| 1280 | */ |
| 1281 | .config_intr = genphy_no_config_intr, |
| 1282 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1283 | .suspend = genphy_suspend, |
| 1284 | .resume = genphy_resume, |
| 1285 | .read_page = mtk_gephy_read_page, |
| 1286 | .write_page = mtk_gephy_write_page, |
| 1287 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1288 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1289 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1290 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1291 | .name = "MediaTek MT7981 PHY", |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1292 | .probe = mt7981_phy_probe, |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1293 | .config_intr = genphy_no_config_intr, |
| 1294 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1295 | .suspend = genphy_suspend, |
| 1296 | .resume = genphy_resume, |
| 1297 | .read_page = mtk_gephy_read_page, |
| 1298 | .write_page = mtk_gephy_write_page, |
| 1299 | }, |
| 1300 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1301 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1302 | .name = "MediaTek MT7988 PHY", |
| 1303 | .probe = mt7988_phy_probe, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1304 | .config_intr = genphy_no_config_intr, |
| 1305 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1306 | .suspend = genphy_suspend, |
| 1307 | .resume = genphy_resume, |
| 1308 | .read_page = mtk_gephy_read_page, |
| 1309 | .write_page = mtk_gephy_write_page, |
| 1310 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1311 | #endif |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1312 | }; |
| 1313 | |
| 1314 | module_phy_driver(mtk_gephy_driver); |
| 1315 | |
| 1316 | static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { |
| 1317 | { PHY_ID_MATCH_VENDOR(0x03a29400) }, |
| 1318 | { } |
| 1319 | }; |
| 1320 | |
| 1321 | MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1322 | MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); |
| 1323 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1324 | MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>"); |
| 1325 | MODULE_LICENSE("GPL"); |
| 1326 | |
| 1327 | MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); |