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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 42c5faaf90388c0f0ce3c0327a17ad207978d465 / . / target / linux / mediatek / patches-5.4 / 999-2720-net-dsa-phy-coverity-scan.patch
blob: dfdb019968072cfff91b1ea845d2605f68938876 [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]1From 98719219a038adac88f2fae9caaecb7e84704d09 Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:32 +0800
4Subject: [PATCH] [networking][999-2720-net-dsa-phy-coverity-scan.patch]
5
6---
7 drivers/net/dsa/mt7530.c | 4 ++-
8 drivers/net/dsa/mt7531_phy.c | 56 +++++++++++++++++++-----------------
9 2 files changed, 32 insertions(+), 28 deletions(-)
10
11diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
12index 290a2e77a..21fa3e300 100644
13--- a/drivers/net/dsa/mt7530.c
14+++ b/drivers/net/dsa/mt7530.c
15@@ -2477,7 +2477,7 @@ static int
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]16 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
17 {
18 struct mt7530_priv *priv = ds->priv;
19- phy_interface_t interface;
20+ phy_interface_t interface = PHY_INTERFACE_MODE_NA;
21 int speed;
22
23 switch (port) {
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]24@@ -2497,6 +2497,8 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]25 priv->p6_interface = interface;
26 break;
27 };
28+ if (interface == PHY_INTERFACE_MODE_NA)
29+ dev_err(priv->dev, "invalid interface\n");
30
31 if (interface == PHY_INTERFACE_MODE_2500BASEX)
32 speed = SPEED_2500;
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]33diff --git a/drivers/net/dsa/mt7531_phy.c b/drivers/net/dsa/mt7531_phy.c
34index a5c1e7d54..aaa03c678 100644
35--- a/drivers/net/dsa/mt7531_phy.c
36+++ b/drivers/net/dsa/mt7531_phy.c
37@@ -252,7 +252,7 @@ static int ge_cal_rext(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]38 u16 dev1e_17a_tmp, dev1e_e0_tmp;
39
40 /* *** Iext/Rext Cal start ************ */
41- all_ana_cal_status = ANACAL_INIT;
42+ //all_ana_cal_status = ANACAL_INIT;
43 /* analog calibration enable, Rext calibration enable */
44 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
45 /* 1e_dc[0]:rg_txvos_calen */
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]46@@ -296,7 +296,7 @@ static int ge_cal_rext(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]47 all_ana_cal_status = ANACAL_FINISH;
48 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
49 } else {
50- dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
51+ //dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
52 dev1e_e0_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0xe0);
53 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
54 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]55@@ -718,32 +718,34 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]56 } else if (phyaddr == 1) {
57 if (calibration_pair == ANACAL_PAIR_A)
58 tx_amp_temp = tx_amp_temp - 1;
59- else if(calibration_pair == ANACAL_PAIR_B)
60- tx_amp_temp = tx_amp_temp ;
61+ //else if(calibration_pair == ANACAL_PAIR_B)
62+ // tx_amp_temp = tx_amp_temp;
63 else if(calibration_pair == ANACAL_PAIR_C)
64 tx_amp_temp = tx_amp_temp - 1;
65 else if(calibration_pair == ANACAL_PAIR_D)
66 tx_amp_temp = tx_amp_temp - 1;
67 } else if (phyaddr == 2) {
68- if (calibration_pair == ANACAL_PAIR_A)
69- tx_amp_temp = tx_amp_temp;
70- else if(calibration_pair == ANACAL_PAIR_B)
71+ //if (calibration_pair == ANACAL_PAIR_A)
72+ // tx_amp_temp = tx_amp_temp;
73+ //else if(calibration_pair == ANACAL_PAIR_B)
74+ if(calibration_pair == ANACAL_PAIR_B)
75 tx_amp_temp = tx_amp_temp - 1;
76- else if(calibration_pair == ANACAL_PAIR_C)
77- tx_amp_temp = tx_amp_temp;
78+ //else if(calibration_pair == ANACAL_PAIR_C)
79+ // tx_amp_temp = tx_amp_temp;
80 else if(calibration_pair == ANACAL_PAIR_D)
81 tx_amp_temp = tx_amp_temp - 1;
82- } else if (phyaddr == 3) {
83- tx_amp_temp = tx_amp_temp;
84+ //} else if (phyaddr == 3) {
85+ // tx_amp_temp = tx_amp_temp;
86 } else if (phyaddr == 4) {
87- if (calibration_pair == ANACAL_PAIR_A)
88- tx_amp_temp = tx_amp_temp;
89- else if(calibration_pair == ANACAL_PAIR_B)
90+ //if (calibration_pair == ANACAL_PAIR_A)
91+ // tx_amp_temp = tx_amp_temp;
92+ //else if(calibration_pair == ANACAL_PAIR_B)
93+ if(calibration_pair == ANACAL_PAIR_B)
94 tx_amp_temp = tx_amp_temp - 1;
95- else if(calibration_pair == ANACAL_PAIR_C)
96- tx_amp_temp = tx_amp_temp;
97- else if(calibration_pair == ANACAL_PAIR_D)
98- tx_amp_temp = tx_amp_temp;
99+ //else if(calibration_pair == ANACAL_PAIR_C)
100+ // tx_amp_temp = tx_amp_temp;
101+ //else if(calibration_pair == ANACAL_PAIR_D)
102+ // tx_amp_temp = tx_amp_temp;
103 }
104 reg_temp = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
105 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]106@@ -858,7 +860,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]107 reg_backup = 0x0000;
108 reg_backup |= ((tx_amp_temp << 10) | (tx_amp_temp << 0));
109 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x12, reg_backup);
110- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
111+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
112 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
113 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
114 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]115@@ -866,7 +868,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]116 reg_backup = (reg_backup & (~0x3f));
117 reg_backup |= (tx_amp_temp << 0);
118 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x16, reg_backup);
119- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
120+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
121 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
122 }
123 else if(calibration_pair == ANACAL_PAIR_B){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]124@@ -876,7 +878,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]125 reg_backup = 0x0000;
126 reg_backup |= ((tx_amp_temp << 8) | (tx_amp_temp << 0));
127 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x17, reg_backup);
128- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
129+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
130 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
131 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
132 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]133@@ -884,7 +886,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]134 reg_backup = (reg_backup & (~0x3f));
135 reg_backup |= (tx_amp_temp << 0);
136 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x18, reg_backup);
137- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
138+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
139 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
140 }
141 else if(calibration_pair == ANACAL_PAIR_C){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]142@@ -894,7 +896,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]143 reg_backup = (reg_backup & (~0x3f00));
144 reg_backup |= (tx_amp_temp << 8);
145 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x19, reg_backup);
146- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
147+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
148 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
149 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
150 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]151@@ -902,7 +904,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]152 reg_backup = (reg_backup & (~0x3f));
153 reg_backup |= (tx_amp_temp << 0);
154 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x20, reg_backup);
155- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
156+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
157 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
158 }
159 else if(calibration_pair == ANACAL_PAIR_D){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]160@@ -912,7 +914,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]161 reg_backup = (reg_backup & (~0x3f00));
162 reg_backup |= (tx_amp_temp << 8);
163 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x21, reg_backup);
164- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
165+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
166 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
167 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
168 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]169@@ -920,7 +922,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]170 reg_backup = (reg_backup & (~0x3f));
171 reg_backup |= (tx_amp_temp << 0);
172 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x22, reg_backup);
173- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
174+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
175 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
176 }
177
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]178@@ -1352,7 +1354,7 @@ static void mt7531_eee_setting(struct dsa_switch *ds, u32 port)
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]179
180 int mt7531_phy_setup(struct dsa_switch *ds)
181 {
182- int ret;
183+ int ret = 0;
184 int i;
185
developer0b16f962022-12-22 12:25:34 +0800[diff] [blame]186 mt7531_phy_setting(ds);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]187--
1882.34.1
189