[][openwrt][update the patches in accordance with the new naming rules]
[Description]
Change all mtk patches in accordance with the new naming rules
"999-20xx-" : Basic Part
"999-21xx-" : Slow Speed I/O
"999-22xx-" : Slow Speed I/O
"999-23xx-" : SPI & Storage
"999-24xx-" : SPI & Storage
"999-25xx-" : Advanced features
"999-26xx-" : High Speed I/O
"999-27xx-" : Networking
"999-28xx-" : MISC
"999-29xx-" : Uncategorized
[Release-log]
N/A
Change-Id: I245da3b0e5b7299b42473c20cc6f0899cffc1ad2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7530987
diff --git a/target/linux/mediatek/patches-5.4/999-2720-net-dsa-phy-coverity-scan.patch b/target/linux/mediatek/patches-5.4/999-2720-net-dsa-phy-coverity-scan.patch
new file mode 100644
index 0000000..dfdb019
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/999-2720-net-dsa-phy-coverity-scan.patch
@@ -0,0 +1,189 @@
+From 98719219a038adac88f2fae9caaecb7e84704d09 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 2 Jun 2023 13:06:32 +0800
+Subject: [PATCH] [networking][999-2720-net-dsa-phy-coverity-scan.patch]
+
+---
+ drivers/net/dsa/mt7530.c | 4 ++-
+ drivers/net/dsa/mt7531_phy.c | 56 +++++++++++++++++++-----------------
+ 2 files changed, 32 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
+index 290a2e77a..21fa3e300 100644
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2477,7 +2477,7 @@ static int
+ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- phy_interface_t interface;
++ phy_interface_t interface = PHY_INTERFACE_MODE_NA;
+ int speed;
+
+ switch (port) {
+@@ -2497,6 +2497,8 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
+ priv->p6_interface = interface;
+ break;
+ };
++ if (interface == PHY_INTERFACE_MODE_NA)
++ dev_err(priv->dev, "invalid interface\n");
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ speed = SPEED_2500;
+diff --git a/drivers/net/dsa/mt7531_phy.c b/drivers/net/dsa/mt7531_phy.c
+index a5c1e7d54..aaa03c678 100644
+--- a/drivers/net/dsa/mt7531_phy.c
++++ b/drivers/net/dsa/mt7531_phy.c
+@@ -252,7 +252,7 @@ static int ge_cal_rext(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ u16 dev1e_17a_tmp, dev1e_e0_tmp;
+
+ /* *** Iext/Rext Cal start ************ */
+- all_ana_cal_status = ANACAL_INIT;
++ //all_ana_cal_status = ANACAL_INIT;
+ /* analog calibration enable, Rext calibration enable */
+ /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
+ /* 1e_dc[0]:rg_txvos_calen */
+@@ -296,7 +296,7 @@ static int ge_cal_rext(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ all_ana_cal_status = ANACAL_FINISH;
+ //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
+ } else {
+- dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
++ //dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
+ dev1e_e0_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0xe0);
+ if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
+ all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
+@@ -718,32 +718,34 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ } else if (phyaddr == 1) {
+ if (calibration_pair == ANACAL_PAIR_A)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_B)
+- tx_amp_temp = tx_amp_temp ;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_C)
+ tx_amp_temp = tx_amp_temp - 1;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+ } else if (phyaddr == 2) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+- } else if (phyaddr == 3) {
+- tx_amp_temp = tx_amp_temp;
++ //} else if (phyaddr == 3) {
++ // tx_amp_temp = tx_amp_temp;
+ } else if (phyaddr == 4) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_D)
+- tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_D)
++ // tx_amp_temp = tx_amp_temp;
+ }
+ reg_temp = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
+@@ -858,7 +860,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = 0x0000;
+ reg_backup |= ((tx_amp_temp << 10) | (tx_amp_temp << 0));
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x12, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
+ //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -866,7 +868,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x16, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
+ //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_B){
+@@ -876,7 +878,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = 0x0000;
+ reg_backup |= ((tx_amp_temp << 8) | (tx_amp_temp << 0));
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x17, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
+ //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -884,7 +886,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x18, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
+ //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_C){
+@@ -894,7 +896,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (tx_amp_temp << 8);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x19, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
+ //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -902,7 +904,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x20, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
+ //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_D){
+@@ -912,7 +914,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (tx_amp_temp << 8);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x21, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
+ //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -920,7 +922,7 @@ static int ge_cal_tx_amp(struct dsa_switch *ds, u8 phyaddr, u32 delay)
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x22, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
+ //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ }
+
+@@ -1352,7 +1354,7 @@ static void mt7531_eee_setting(struct dsa_switch *ds, u32 port)
+
+ int mt7531_phy_setup(struct dsa_switch *ds)
+ {
+- int ret;
++ int ret = 0;
+ int i;
+
+ mt7531_phy_setting(ds);
+--
+2.34.1
+