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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 91044d5bb454325e0761bb85a04a06c5f4cd08ca / . / target / linux / mediatek / patches-5.4 / 752-net-dsa-phy-coverity-scan.patch
blob: e2c731f8aa41833a91ca86b04badc02c3de4e99d [file] [log] [blame]
developer91044d52022-11-28 10:01:04 +0800[diff] [blame^]1diff -Naur a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
2--- a/drivers/net/dsa/mt7530.c 2022-11-25 14:10:39.452491570 +0800
3+++ b/drivers/net/dsa/mt7530.c 2022-11-28 09:47:11.157096408 +0800
4@@ -2476,7 +2476,7 @@
5 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
6 {
7 struct mt7530_priv *priv = ds->priv;
8- phy_interface_t interface;
9+ phy_interface_t interface = PHY_INTERFACE_MODE_NA;
10 int speed;
11
12 switch (port) {
13@@ -2496,6 +2496,8 @@
14 priv->p6_interface = interface;
15 break;
16 };
17+ if (interface == PHY_INTERFACE_MODE_NA)
18+ dev_err(priv->dev, "invalid interface\n");
19
20 if (interface == PHY_INTERFACE_MODE_2500BASEX)
21 speed = SPEED_2500;
22diff -Naur a/drivers/net/dsa/mt7531_phy.c b/drivers/net/dsa/mt7531_phy.c
23--- a/drivers/net/dsa/mt7531_phy.c 2022-11-25 14:10:47.032465430 +0800
24+++ b/drivers/net/dsa/mt7531_phy.c 2022-11-29 09:56:05.024665073 +0800
25@@ -252,7 +252,7 @@
26 u16 dev1e_17a_tmp, dev1e_e0_tmp;
27
28 /* *** Iext/Rext Cal start ************ */
29- all_ana_cal_status = ANACAL_INIT;
30+ //all_ana_cal_status = ANACAL_INIT;
31 /* analog calibration enable, Rext calibration enable */
32 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
33 /* 1e_dc[0]:rg_txvos_calen */
34@@ -296,7 +296,7 @@
35 all_ana_cal_status = ANACAL_FINISH;
36 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
37 } else {
38- dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
39+ //dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
40 dev1e_e0_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0xe0);
41 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
42 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
43@@ -718,32 +718,34 @@
44 } else if (phyaddr == 1) {
45 if (calibration_pair == ANACAL_PAIR_A)
46 tx_amp_temp = tx_amp_temp - 1;
47- else if(calibration_pair == ANACAL_PAIR_B)
48- tx_amp_temp = tx_amp_temp ;
49+ //else if(calibration_pair == ANACAL_PAIR_B)
50+ // tx_amp_temp = tx_amp_temp;
51 else if(calibration_pair == ANACAL_PAIR_C)
52 tx_amp_temp = tx_amp_temp - 1;
53 else if(calibration_pair == ANACAL_PAIR_D)
54 tx_amp_temp = tx_amp_temp - 1;
55 } else if (phyaddr == 2) {
56- if (calibration_pair == ANACAL_PAIR_A)
57- tx_amp_temp = tx_amp_temp;
58- else if(calibration_pair == ANACAL_PAIR_B)
59+ //if (calibration_pair == ANACAL_PAIR_A)
60+ // tx_amp_temp = tx_amp_temp;
61+ //else if(calibration_pair == ANACAL_PAIR_B)
62+ if(calibration_pair == ANACAL_PAIR_B)
63 tx_amp_temp = tx_amp_temp - 1;
64- else if(calibration_pair == ANACAL_PAIR_C)
65- tx_amp_temp = tx_amp_temp;
66+ //else if(calibration_pair == ANACAL_PAIR_C)
67+ // tx_amp_temp = tx_amp_temp;
68 else if(calibration_pair == ANACAL_PAIR_D)
69 tx_amp_temp = tx_amp_temp - 1;
70- } else if (phyaddr == 3) {
71- tx_amp_temp = tx_amp_temp;
72+ //} else if (phyaddr == 3) {
73+ // tx_amp_temp = tx_amp_temp;
74 } else if (phyaddr == 4) {
75- if (calibration_pair == ANACAL_PAIR_A)
76- tx_amp_temp = tx_amp_temp;
77- else if(calibration_pair == ANACAL_PAIR_B)
78+ //if (calibration_pair == ANACAL_PAIR_A)
79+ // tx_amp_temp = tx_amp_temp;
80+ //else if(calibration_pair == ANACAL_PAIR_B)
81+ if(calibration_pair == ANACAL_PAIR_B)
82 tx_amp_temp = tx_amp_temp - 1;
83- else if(calibration_pair == ANACAL_PAIR_C)
84- tx_amp_temp = tx_amp_temp;
85- else if(calibration_pair == ANACAL_PAIR_D)
86- tx_amp_temp = tx_amp_temp;
87+ //else if(calibration_pair == ANACAL_PAIR_C)
88+ // tx_amp_temp = tx_amp_temp;
89+ //else if(calibration_pair == ANACAL_PAIR_D)
90+ // tx_amp_temp = tx_amp_temp;
91 }
92 reg_temp = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
93 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
94@@ -858,7 +860,7 @@
95 reg_backup = 0x0000;
96 reg_backup |= ((tx_amp_temp << 10) | (tx_amp_temp << 0));
97 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x12, reg_backup);
98- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
99+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
100 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
101 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
102 reg_tmp = ((reg_backup & 0x3f) >> 0);
103@@ -866,7 +868,7 @@
104 reg_backup = (reg_backup & (~0x3f));
105 reg_backup |= (tx_amp_temp << 0);
106 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x16, reg_backup);
107- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
108+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
109 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
110 }
111 else if(calibration_pair == ANACAL_PAIR_B){
112@@ -876,7 +878,7 @@
113 reg_backup = 0x0000;
114 reg_backup |= ((tx_amp_temp << 8) | (tx_amp_temp << 0));
115 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x17, reg_backup);
116- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
117+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
118 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
119 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
120 reg_tmp = ((reg_backup & 0x3f) >> 0);
121@@ -884,7 +886,7 @@
122 reg_backup = (reg_backup & (~0x3f));
123 reg_backup |= (tx_amp_temp << 0);
124 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x18, reg_backup);
125- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
126+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
127 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
128 }
129 else if(calibration_pair == ANACAL_PAIR_C){
130@@ -894,7 +896,7 @@
131 reg_backup = (reg_backup & (~0x3f00));
132 reg_backup |= (tx_amp_temp << 8);
133 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x19, reg_backup);
134- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
135+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
136 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
137 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
138 reg_tmp = ((reg_backup & 0x3f) >> 0);
139@@ -902,7 +904,7 @@
140 reg_backup = (reg_backup & (~0x3f));
141 reg_backup |= (tx_amp_temp << 0);
142 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x20, reg_backup);
143- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
144+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
145 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
146 }
147 else if(calibration_pair == ANACAL_PAIR_D){
148@@ -912,7 +914,7 @@
149 reg_backup = (reg_backup & (~0x3f00));
150 reg_backup |= (tx_amp_temp << 8);
151 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x21, reg_backup);
152- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
153+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
154 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
155 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
156 reg_tmp = ((reg_backup & 0x3f) >> 0);
157@@ -920,7 +922,7 @@
158 reg_backup = (reg_backup & (~0x3f));
159 reg_backup |= (tx_amp_temp << 0);
160 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x22, reg_backup);
161- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
162+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
163 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
164 }
165
166@@ -1352,7 +1354,7 @@
167
168 int mt7531_phy_setup(struct dsa_switch *ds)
169 {
170- int ret;
171+ int ret = 0;
172 int i;
173
174 mt7531_phy_setting(ds);
175diff -Naur a/drivers/net/phy/mtk/mt753x/mt7531.c b/drivers/net/phy/mtk/mt753x/mt7531.c
176--- a/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:11:51.944272549 +0800
177+++ b/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:19:49.970820719 +0800
178@@ -1062,6 +1062,7 @@
179 u32 pmcr;
180 u32 speed;
181
182+ pdev = container_of(gsw->dev, struct platform_device, dev);
183 switch_node = of_find_node_by_name(NULL, "switch0");
184 if (switch_node == NULL) {
185 dev_err(&pdev->dev, "switch node invaild\n");
186@@ -1074,7 +1075,6 @@
187 return -EIO;
188 }
189
190- pdev = container_of(gsw->dev, struct platform_device, dev);
191 gsw->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
192 "mediatek,sysctrl");
193 if (IS_ERR(gsw->sysctrl_base)) {
194diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c
195--- a/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:12:06.308223474 +0800
196+++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:21:52.038450276 +0800
197@@ -49,6 +49,9 @@
198 case MAC_SPD_2500:
199 speed = "2.5Gbps";
200 break;
201+ default:
202+ dev_info(gsw->dev, "Invalid speed\n");
203+ return;
204 }
205
206 if (pmsr & MAC_LNK_STS) {
207diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
208--- a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 14:12:29.064162894 +0800
209+++ b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 17:04:01.973949052 +0800
210@@ -495,7 +495,7 @@
211 struct device_node *np = gsw->dev->of_node;
212 struct reset_control *rstc;
213 int mcm;
214- int ret = -EINVAL;
215+ int ret;
216
217 mcm = of_property_read_bool(np, "mediatek,mcm");
218 if (mcm) {
219diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_nl.c b/drivers/net/phy/mtk/mt753x/mt753x_nl.c
220--- a/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 14:12:12.292202033 +0800
221+++ b/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 17:01:26.881930912 +0800
222@@ -75,8 +75,10 @@
223 len = snprintf(buf, sizeof(buf),
224 "id: %d, model: %s, node: %s\n",
225 gsw->id, gsw->name, gsw->dev->of_node->name);
226- strncat(buff, buf, size - total);
227- total += len;
228+ if (len == strlen(buf)) {
229+ strncat(buff, buf, size - total);
230+ total += len;
231+ }
232 }
233
234 mt753x_put_gsw();
235diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
236--- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-25 14:12:34.160149995 +0800
237+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-29 14:12:28.261884707 +0800
238@@ -141,7 +141,7 @@
239 u16 dev1e_17a_tmp, dev1e_e0_tmp;
240
241 /* *** Iext/Rext Cal start ************ */
242- all_ana_cal_status = ANACAL_INIT;
243+ //all_ana_cal_status = ANACAL_INIT;
244 /* analog calibration enable, Rext calibration enable */
245 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
246 /* 1e_dc[0]:rg_txvos_calen */
247@@ -185,7 +185,7 @@
248 all_ana_cal_status = ANACAL_FINISH;
249 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
250 } else {
251- dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
252+ //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
253 dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
254 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
255 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
256@@ -580,33 +580,35 @@
257 } else if (phyaddr == 1) {
258 if (calibration_pair == ANACAL_PAIR_A)
259 tx_amp_temp = tx_amp_temp - 1;
260- else if(calibration_pair == ANACAL_PAIR_B)
261- tx_amp_temp = tx_amp_temp ;
262+ //else if(calibration_pair == ANACAL_PAIR_B)
263+ // tx_amp_temp = tx_amp_temp;
264 else if(calibration_pair == ANACAL_PAIR_C)
265 tx_amp_temp = tx_amp_temp - 1;
266 else if(calibration_pair == ANACAL_PAIR_D)
267 tx_amp_temp = tx_amp_temp - 1;
268 } else if (phyaddr == 2) {
269- if (calibration_pair == ANACAL_PAIR_A)
270- tx_amp_temp = tx_amp_temp;
271- else if(calibration_pair == ANACAL_PAIR_B)
272+ //if (calibration_pair == ANACAL_PAIR_A)
273+ // tx_amp_temp = tx_amp_temp;
274+ //else if(calibration_pair == ANACAL_PAIR_B)
275+ if(calibration_pair == ANACAL_PAIR_B)
276 tx_amp_temp = tx_amp_temp - 1;
277- else if(calibration_pair == ANACAL_PAIR_C)
278- tx_amp_temp = tx_amp_temp;
279+ //else if(calibration_pair == ANACAL_PAIR_C)
280+ // tx_amp_temp = tx_amp_temp;
281 else if(calibration_pair == ANACAL_PAIR_D)
282 tx_amp_temp = tx_amp_temp - 1;
283- } else if (phyaddr == 3) {
284- tx_amp_temp = tx_amp_temp;
285+ //} else if (phyaddr == 3) {
286+ // tx_amp_temp = tx_amp_temp;
287 } else if (phyaddr == 4) {
288- if (calibration_pair == ANACAL_PAIR_A)
289- tx_amp_temp = tx_amp_temp;
290- else if(calibration_pair == ANACAL_PAIR_B)
291+ //if (calibration_pair == ANACAL_PAIR_A)
292+ // tx_amp_temp = tx_amp_temp;
293+ //else if(calibration_pair == ANACAL_PAIR_B)
294+ if(calibration_pair == ANACAL_PAIR_B)
295 tx_amp_temp = tx_amp_temp - 1;
296- else if(calibration_pair == ANACAL_PAIR_C)
297- tx_amp_temp = tx_amp_temp;
298- else if(calibration_pair == ANACAL_PAIR_D)
299- tx_amp_temp = tx_amp_temp;
300- }
301+ //else if(calibration_pair == ANACAL_PAIR_C)
302+ // tx_amp_temp = tx_amp_temp;
303+ //else if(calibration_pair == ANACAL_PAIR_D)
304+ // tx_amp_temp = tx_amp_temp;
305+ }
306 reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
307 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
308 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
309@@ -704,7 +706,7 @@
310 reg_backup = 0x0000;
311 reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
312 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
313- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
314+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
315 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
316 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
317 reg_tmp = ((reg_backup & 0x3f) >> 0);
318@@ -712,7 +714,7 @@
319 reg_backup = (reg_backup & (~0x3f));
320 reg_backup |= (reg_tmp << 0);
321 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
322- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
323+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
324 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
325 }
326 else if(calibration_pair == ANACAL_PAIR_B){
327@@ -722,7 +724,7 @@
328 reg_backup = 0x0000;
329 reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
330 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
331- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
332+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
333 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
334 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
335 reg_tmp = ((reg_backup & 0x3f) >> 0);
336@@ -730,7 +732,7 @@
337 reg_backup = (reg_backup & (~0x3f));
338 reg_backup |= (reg_tmp << 0);
339 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
340- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
341+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
342 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
343 }
344 else if(calibration_pair == ANACAL_PAIR_C){
345@@ -740,7 +742,7 @@
346 reg_backup = (reg_backup & (~0x3f00));
347 reg_backup |= (reg_tmp << 8);
348 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
349- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
350+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
351 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
352 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
353 reg_tmp = ((reg_backup & 0x3f) >> 0);
354@@ -748,7 +750,7 @@
355 reg_backup = (reg_backup & (~0x3f));
356 reg_backup |= (reg_tmp << 0);
357 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
358- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
359+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
360 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
361 }
362 else if(calibration_pair == ANACAL_PAIR_D){
363@@ -758,7 +760,7 @@
364 reg_backup = (reg_backup & (~0x3f00));
365 reg_backup |= (reg_tmp << 8);
366 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
367- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
368+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
369 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
370 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
371 reg_tmp = ((reg_backup & 0x3f) >> 0);
372@@ -766,7 +768,7 @@
373 reg_backup = (reg_backup & (~0x3f));
374 reg_backup |= (reg_tmp << 0);
375 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
376- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
377+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
378 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
379 }
380