blob: ee10673e424417be426de1af9d4c47f4ceb39369 [file] [log] [blame]
developer356ecec2022-11-14 10:25:04 +08001From b584c123edfe2965d753d4fc7e77c1ec08f147ea Mon Sep 17 00:00:00 2001
developer964926c2022-09-29 13:32:51 +08002From: Peter Chiu <chui-hao.chiu@mediatek.com>
3Date: Wed, 28 Sep 2022 18:52:54 +0800
developer356ecec2022-11-14 10:25:04 +08004Subject: [PATCH 3010/3011] mt76: mt7915: drop scatter and gather frame
developer964926c2022-09-29 13:32:51 +08005
6The scatter and gather frame may be incorrect because WED and WO may
7send frames to host driver interleaved.
8
9Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
developer887da632022-10-28 09:35:38 +080010Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer964926c2022-09-29 13:32:51 +080011---
12 dma.c | 9 +++++++++
13 dma.h | 1 +
14 mt76.h | 1 +
15 3 files changed, 11 insertions(+)
16
17diff --git a/dma.c b/dma.c
developer356ecec2022-11-14 10:25:04 +080018index a7a4538a..c106ae42 100644
developer964926c2022-09-29 13:32:51 +080019--- a/dma.c
20+++ b/dma.c
developerc226de82022-10-03 12:24:57 +080021@@ -419,6 +419,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
22
developer964926c2022-09-29 13:32:51 +080023 if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
24 *drop = true;
25+
26+ if (*more || (q->flags & MT_QFLAG_WED_FRAG)) {
27+ *drop = true;
28+
29+ if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1))
30+ q->flags &= ~MT_QFLAG_WED_FRAG;
31+ else
32+ q->flags |= MT_QFLAG_WED_FRAG;
33+ }
34 } else {
35 buf_addr = e->dma_addr[0];
36 e->buf = NULL;
37diff --git a/dma.h b/dma.h
developer356ecec2022-11-14 10:25:04 +080038index 083cbca4..221fcc8e 100644
developer964926c2022-09-29 13:32:51 +080039--- a/dma.h
40+++ b/dma.h
41@@ -21,6 +21,7 @@
42 #define MT_DMA_CTL_DROP BIT(14)
developerc226de82022-10-03 12:24:57 +080043
developer964926c2022-09-29 13:32:51 +080044 #define MT_DMA_CTL_TOKEN GENMASK(31, 16)
45+#define MT_DMA_CTL_WO BIT(8)
developerc226de82022-10-03 12:24:57 +080046
developer964926c2022-09-29 13:32:51 +080047 #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
48 #define MT_DMA_PPE_ENTRY GENMASK(30, 16)
49diff --git a/mt76.h b/mt76.h
developer356ecec2022-11-14 10:25:04 +080050index 8011d4ca..9b225510 100644
developer964926c2022-09-29 13:32:51 +080051--- a/mt76.h
52+++ b/mt76.h
53@@ -32,6 +32,7 @@
54 #define MT_QFLAG_WED_RING GENMASK(1, 0)
55 #define MT_QFLAG_WED_TYPE GENMASK(3, 2)
56 #define MT_QFLAG_WED BIT(4)
57+#define MT_QFLAG_WED_FRAG BIT(5)
developerc226de82022-10-03 12:24:57 +080058
developer964926c2022-09-29 13:32:51 +080059 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
60 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
developerc226de82022-10-03 12:24:57 +080061--
developer887da632022-10-28 09:35:38 +0800622.18.0
developer964926c2022-09-29 13:32:51 +080063