blob: 0930bfd863b96581095676ccf458c25f43a3bcfe [file] [log] [blame]
developer964926c2022-09-29 13:32:51 +08001From 53ca78fb2c0a95d0776b41002f6307801cb406df Mon Sep 17 00:00:00 2001
2From: Peter Chiu <chui-hao.chiu@mediatek.com>
3Date: Wed, 28 Sep 2022 18:52:54 +0800
4Subject: [PATCH] mt76: mt7915: drop scatter and gather frame
5
6The scatter and gather frame may be incorrect because WED and WO may
7send frames to host driver interleaved.
8
9Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
10---
11 dma.c | 9 +++++++++
12 dma.h | 1 +
13 mt76.h | 1 +
14 3 files changed, 11 insertions(+)
15
16diff --git a/dma.c b/dma.c
17index 063335e1..e6048024 100644
18--- a/dma.c
19+++ b/dma.c
20@@ -421,6 +421,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
21
22 if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
23 *drop = true;
24+
25+ if (*more || (q->flags & MT_QFLAG_WED_FRAG)) {
26+ *drop = true;
27+
28+ if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1))
29+ q->flags &= ~MT_QFLAG_WED_FRAG;
30+ else
31+ q->flags |= MT_QFLAG_WED_FRAG;
32+ }
33 } else {
34 buf_addr = e->dma_addr[0];
35 e->buf = NULL;
36diff --git a/dma.h b/dma.h
37index 083cbca4..221fcc8e 100644
38--- a/dma.h
39+++ b/dma.h
40@@ -21,6 +21,7 @@
41 #define MT_DMA_CTL_DROP BIT(14)
42
43 #define MT_DMA_CTL_TOKEN GENMASK(31, 16)
44+#define MT_DMA_CTL_WO BIT(8)
45
46 #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
47 #define MT_DMA_PPE_ENTRY GENMASK(30, 16)
48diff --git a/mt76.h b/mt76.h
49index 4958d97c..0311e9ea 100644
50--- a/mt76.h
51+++ b/mt76.h
52@@ -32,6 +32,7 @@
53 #define MT_QFLAG_WED_RING GENMASK(1, 0)
54 #define MT_QFLAG_WED_TYPE GENMASK(3, 2)
55 #define MT_QFLAG_WED BIT(4)
56+#define MT_QFLAG_WED_FRAG BIT(5)
57
58 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
59 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
60--
612.18.0
62