developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 1 | From b5a473223aa9bebafa51b5dd465cf6924871eecf Mon Sep 17 00:00:00 2001 |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Wed, 28 Sep 2022 18:52:54 +0800 |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 4 | Subject: [PATCH 3010/3010] mt76: mt7915: drop scatter and gather frame |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 5 | |
| 6 | The scatter and gather frame may be incorrect because WED and WO may |
| 7 | send frames to host driver interleaved. |
| 8 | |
| 9 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 10 | Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 11 | --- |
| 12 | dma.c | 9 +++++++++ |
| 13 | dma.h | 1 + |
| 14 | mt76.h | 1 + |
| 15 | 3 files changed, 11 insertions(+) |
| 16 | |
| 17 | diff --git a/dma.c b/dma.c |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 18 | index a7a4538..c106ae4 100644 |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 19 | --- a/dma.c |
| 20 | +++ b/dma.c |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 21 | @@ -419,6 +419,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, |
| 22 | |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 23 | if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP)) |
| 24 | *drop = true; |
| 25 | + |
| 26 | + if (*more || (q->flags & MT_QFLAG_WED_FRAG)) { |
| 27 | + *drop = true; |
| 28 | + |
| 29 | + if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1)) |
| 30 | + q->flags &= ~MT_QFLAG_WED_FRAG; |
| 31 | + else |
| 32 | + q->flags |= MT_QFLAG_WED_FRAG; |
| 33 | + } |
| 34 | } else { |
| 35 | buf_addr = e->dma_addr[0]; |
| 36 | e->buf = NULL; |
| 37 | diff --git a/dma.h b/dma.h |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 38 | index 083cbca..221fcc8 100644 |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 39 | --- a/dma.h |
| 40 | +++ b/dma.h |
| 41 | @@ -21,6 +21,7 @@ |
| 42 | #define MT_DMA_CTL_DROP BIT(14) |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 43 | |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 44 | #define MT_DMA_CTL_TOKEN GENMASK(31, 16) |
| 45 | +#define MT_DMA_CTL_WO BIT(8) |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 46 | |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 47 | #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11) |
| 48 | #define MT_DMA_PPE_ENTRY GENMASK(30, 16) |
| 49 | diff --git a/mt76.h b/mt76.h |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 50 | index 14c58bc..e5748f2 100644 |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 51 | --- a/mt76.h |
| 52 | +++ b/mt76.h |
| 53 | @@ -32,6 +32,7 @@ |
| 54 | #define MT_QFLAG_WED_RING GENMASK(1, 0) |
| 55 | #define MT_QFLAG_WED_TYPE GENMASK(3, 2) |
| 56 | #define MT_QFLAG_WED BIT(4) |
| 57 | +#define MT_QFLAG_WED_FRAG BIT(5) |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 58 | |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 59 | #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ |
| 60 | FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 61 | -- |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 62 | 2.18.0 |
developer | 964926c | 2022-09-29 13:32:51 +0800 | [diff] [blame] | 63 | |