developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988A DSA 10G SPIM-NOR RFB"; |
| 12 | compatible = "mediatek,mt7988a-dsa-10g-spim-nor", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | wsys_adie: wsys_adie@0 { |
| 27 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 28 | compatible = "mediatek,rebb-mt7988-adie"; |
| 29 | adie_id = <7976>; |
| 30 | sku_type = <3000>; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | &fan { |
| 35 | pwms = <&pwm 0 50000 0>; |
| 36 | status = "okay"; |
| 37 | }; |
| 38 | |
| 39 | &pwm { |
| 40 | status = "okay"; |
| 41 | }; |
| 42 | |
| 43 | &uart0 { |
| 44 | status = "okay"; |
| 45 | }; |
| 46 | |
| 47 | &spi1 { |
| 48 | pinctrl-names = "default"; |
| 49 | /* pin shared with snfi */ |
| 50 | pinctrl-0 = <&spic_pins>; |
| 51 | status = "disabled"; |
| 52 | }; |
| 53 | |
| 54 | &spi2 { |
| 55 | pinctrl-names = "default"; |
| 56 | pinctrl-0 = <&spi2_flash_pins>; |
| 57 | status = "okay"; |
| 58 | spi_nor@0 { |
| 59 | #address-cells = <1>; |
| 60 | #size-cells = <1>; |
| 61 | compatible = "jedec,spi-nor"; |
| 62 | spi-cal-enable; |
| 63 | spi-cal-mode = "read-data"; |
| 64 | spi-cal-datalen = <7>; |
| 65 | spi-cal-data = /bits/ 8 < |
| 66 | 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ |
| 67 | spi-cal-addrlen = <1>; |
| 68 | spi-cal-addr = /bits/ 32 <0x0>; |
| 69 | reg = <0>; |
| 70 | spi-max-frequency = <52000000>; |
developer | 1e51a74 | 2023-03-14 15:16:01 +0800 | [diff] [blame] | 71 | spi-tx-bus-width = <4>; |
| 72 | spi-rx-bus-width = <4>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 73 | |
| 74 | partition@00000 { |
| 75 | label = "BL2"; |
| 76 | reg = <0x00000 0x0040000>; |
| 77 | }; |
| 78 | partition@40000 { |
| 79 | label = "u-boot-env"; |
| 80 | reg = <0x40000 0x0010000>; |
| 81 | }; |
| 82 | factory: partition@50000 { |
| 83 | label = "Factory"; |
developer | 8f434cd | 2023-02-07 10:29:26 +0800 | [diff] [blame] | 84 | reg = <0x50000 0x0200000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 85 | }; |
developer | 8f434cd | 2023-02-07 10:29:26 +0800 | [diff] [blame] | 86 | partition@250000 { |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 87 | label = "FIP"; |
developer | 8f434cd | 2023-02-07 10:29:26 +0800 | [diff] [blame] | 88 | reg = <0x250000 0x0080000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 89 | }; |
developer | 8f434cd | 2023-02-07 10:29:26 +0800 | [diff] [blame] | 90 | partition@2D0000 { |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 91 | label = "firmware"; |
developer | 8f434cd | 2023-02-07 10:29:26 +0800 | [diff] [blame] | 92 | reg = <0x2D0000 0x1D30000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 93 | }; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | &pcie0 { |
| 98 | pinctrl-names = "default"; |
| 99 | pinctrl-0 = <&pcie0_pins>; |
| 100 | status = "okay"; |
| 101 | }; |
| 102 | |
| 103 | &pcie1 { |
| 104 | pinctrl-names = "default"; |
| 105 | pinctrl-0 = <&pcie1_pins>; |
| 106 | status = "okay"; |
| 107 | }; |
| 108 | |
| 109 | &pcie2 { |
| 110 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = <&pcie2_pins>; |
| 112 | status = "disabled"; |
| 113 | }; |
| 114 | |
| 115 | &pcie3 { |
| 116 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pcie3_pins>; |
| 118 | status = "okay"; |
| 119 | }; |
| 120 | |
| 121 | &pio { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 122 | mdio0_pins: mdio0-pins { |
| 123 | mux { |
| 124 | function = "mdio"; |
| 125 | groups = "mdc_mdio0"; |
| 126 | }; |
| 127 | |
| 128 | conf { |
| 129 | groups = "mdc_mdio0"; |
| 130 | drive-strength = <MTK_DRIVE_8mA>; |
| 131 | }; |
| 132 | }; |
| 133 | |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 134 | gbe_led0_pins: gbe-pins { |
| 135 | mux { |
| 136 | function = "led"; |
| 137 | groups = "gbe_led0"; |
| 138 | }; |
| 139 | }; |
| 140 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 141 | pcie0_pins: pcie0-pins { |
| 142 | mux { |
| 143 | function = "pcie"; |
| 144 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 145 | "pcie_wake_n0_0"; |
| 146 | }; |
| 147 | }; |
| 148 | |
| 149 | pcie1_pins: pcie1-pins { |
| 150 | mux { |
| 151 | function = "pcie"; |
| 152 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 153 | "pcie_wake_n1_0"; |
| 154 | }; |
| 155 | }; |
| 156 | |
| 157 | pcie2_pins: pcie2-pins { |
| 158 | mux { |
| 159 | function = "pcie"; |
| 160 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 161 | "pcie_wake_n2_0"; |
| 162 | }; |
| 163 | }; |
| 164 | |
| 165 | pcie3_pins: pcie3-pins { |
| 166 | mux { |
| 167 | function = "pcie"; |
| 168 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 169 | "pcie_wake_n3_0"; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | spic_pins: spi1-pins { |
| 174 | mux { |
| 175 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 176 | groups = "spi1"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 177 | }; |
| 178 | }; |
| 179 | |
| 180 | spi2_flash_pins: spi2-pins { |
| 181 | mux { |
| 182 | function = "spi"; |
| 183 | groups = "spi2", "spi2_wp_hold"; |
| 184 | }; |
| 185 | }; |
| 186 | }; |
| 187 | |
| 188 | &watchdog { |
| 189 | status = "disabled"; |
| 190 | }; |
| 191 | |
| 192 | ð { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 193 | pinctrl-names = "default"; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 194 | pinctrl-0 = <&mdio0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 195 | status = "okay"; |
| 196 | |
| 197 | gmac0: mac@0 { |
| 198 | compatible = "mediatek,eth-mac"; |
| 199 | reg = <0>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 200 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 201 | phy-mode = "10gbase-kr"; |
| 202 | |
| 203 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 204 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 205 | full-duplex; |
| 206 | pause; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | gmac1: mac@1 { |
| 211 | compatible = "mediatek,eth-mac"; |
| 212 | reg = <1>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 213 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 214 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 215 | phy-handle = <&phy0>; |
| 216 | }; |
| 217 | |
| 218 | gmac2: mac@2 { |
| 219 | compatible = "mediatek,eth-mac"; |
| 220 | reg = <2>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 221 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 222 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 223 | phy-handle = <&phy1>; |
| 224 | }; |
| 225 | |
| 226 | mdio: mdio-bus { |
| 227 | #address-cells = <1>; |
| 228 | #size-cells = <0>; |
developer | c4d8da7 | 2023-03-16 14:37:28 +0800 | [diff] [blame] | 229 | clock-frequency = <10500000>; |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 230 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 231 | phy0: ethernet-phy@0 { |
| 232 | reg = <0>; |
| 233 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 234 | reset-gpios = <&pio 72 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 235 | reset-assert-us = <100000>; |
| 236 | reset-deassert-us = <221000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | phy1: ethernet-phy@8 { |
| 240 | reg = <8>; |
| 241 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 242 | reset-gpios = <&pio 71 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 243 | reset-assert-us = <100000>; |
| 244 | reset-deassert-us = <221000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | switch@0 { |
| 248 | compatible = "mediatek,mt7988"; |
| 249 | reg = <31>; |
| 250 | ports { |
| 251 | #address-cells = <1>; |
| 252 | #size-cells = <0>; |
| 253 | |
| 254 | port@0 { |
| 255 | reg = <0>; |
| 256 | label = "lan0"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 257 | phy-mode = "gmii"; |
| 258 | phy-handle = <&sphy0>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | port@1 { |
| 262 | reg = <1>; |
| 263 | label = "lan1"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 264 | phy-mode = "gmii"; |
| 265 | phy-handle = <&sphy1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | port@2 { |
| 269 | reg = <2>; |
| 270 | label = "lan2"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 271 | phy-mode = "gmii"; |
| 272 | phy-handle = <&sphy2>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | port@3 { |
| 276 | reg = <3>; |
| 277 | label = "lan3"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 278 | phy-mode = "gmii"; |
| 279 | phy-handle = <&sphy3>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | port@6 { |
| 283 | reg = <6>; |
| 284 | label = "cpu"; |
| 285 | ethernet = <&gmac0>; |
| 286 | phy-mode = "10gbase-kr"; |
| 287 | |
| 288 | fixed-link { |
| 289 | speed = <10000>; |
| 290 | full-duplex; |
| 291 | pause; |
| 292 | }; |
| 293 | }; |
| 294 | }; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 295 | |
| 296 | mdio { |
| 297 | compatible = "mediatek,dsa-slave-mdio"; |
| 298 | #address-cells = <1>; |
| 299 | #size-cells = <0>; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 300 | pinctrl-names = "default"; |
| 301 | pinctrl-0 = <&gbe_led0_pins>; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 302 | |
| 303 | sphy0: switch_phy0@0 { |
| 304 | compatible = "ethernet-phy-id03a2.9481"; |
| 305 | reg = <0>; |
| 306 | phy-mode = "gmii"; |
| 307 | rext = "efuse"; |
| 308 | tx_r50 = "efuse"; |
| 309 | nvmem-cells = <&phy_calibration_p0>; |
| 310 | nvmem-cell-names = "phy-cal-data"; |
| 311 | }; |
| 312 | |
| 313 | sphy1: switch_phy1@1 { |
| 314 | compatible = "ethernet-phy-id03a2.9481"; |
| 315 | reg = <1>; |
| 316 | phy-mode = "gmii"; |
| 317 | rext = "efuse"; |
| 318 | tx_r50 = "efuse"; |
| 319 | nvmem-cells = <&phy_calibration_p1>; |
| 320 | nvmem-cell-names = "phy-cal-data"; |
| 321 | }; |
| 322 | |
| 323 | sphy2: switch_phy2@2 { |
| 324 | compatible = "ethernet-phy-id03a2.9481"; |
| 325 | reg = <2>; |
| 326 | phy-mode = "gmii"; |
| 327 | rext = "efuse"; |
| 328 | tx_r50 = "efuse"; |
| 329 | nvmem-cells = <&phy_calibration_p2>; |
| 330 | nvmem-cell-names = "phy-cal-data"; |
| 331 | }; |
| 332 | |
| 333 | sphy3: switch_phy3@3 { |
| 334 | compatible = "ethernet-phy-id03a2.9481"; |
| 335 | reg = <3>; |
| 336 | phy-mode = "gmii"; |
| 337 | rext = "efuse"; |
| 338 | tx_r50 = "efuse"; |
| 339 | nvmem-cells = <&phy_calibration_p3>; |
| 340 | nvmem-cell-names = "phy-cal-data"; |
| 341 | }; |
| 342 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 343 | }; |
| 344 | }; |
| 345 | }; |
| 346 | |
| 347 | &hnat { |
| 348 | mtketh-wan = "eth1"; |
| 349 | mtketh-lan = "lan"; |
| 350 | mtketh-lan2 = "eth2"; |
| 351 | mtketh-max-gmac = <3>; |
| 352 | status = "okay"; |
| 353 | }; |
| 354 | |
| 355 | &wed { |
| 356 | dy_txbm_enable = "true"; |
| 357 | dy_txbm_budge = <8>; |
| 358 | txbm_init_sz = <10>; |
| 359 | status = "okay"; |
| 360 | }; |