blob: baec4abd1cfbe670687a343574de3d86e577d674 [file] [log] [blame]
developer691e73f2021-06-28 19:41:35 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developer691e73f2021-06-28 19:41:35 +08005/ {
6 model = "MediaTek MT7986a RFB";
7 compatible = "mediatek,mt7986a-2500wan-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 sound {
18 compatible = "mediatek,mt7986-wm8960-machine";
19 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developer691e73f2021-06-28 19:41:35 +080027};
28
developer209e52d2022-06-30 11:32:57 +080029&fan {
30 pwms = <&pwm 1 50000 0>;
31 status = "disabled";
32};
33
developer565bacb2021-09-28 21:26:32 +080034&pwm {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
developer691e73f2021-06-28 19:41:35 +080037 status = "okay";
developer565bacb2021-09-28 21:26:32 +080038};
developer5b91be72021-09-27 14:03:07 +080039
developer565bacb2021-09-28 21:26:32 +080040&uart0 {
41 status = "okay";
42};
43
44&uart1 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&uart1_pins>;
47 status = "okay";
48};
49
50&uart2 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&uart2_pins>;
developer8b1069e2022-08-26 17:49:39 +080053 status = "disabled";
developer565bacb2021-09-28 21:26:32 +080054};
55
56&i2c0 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&i2c_pins>;
59 status = "okay";
60
61 wm8960: wm8960@1a {
62 compatible = "wlf,wm8960";
63 reg = <0x1a>;
developer5b91be72021-09-27 14:03:07 +080064 };
65};
66
developer565bacb2021-09-28 21:26:32 +080067&auxadc {
68 status = "okay";
developer5b91be72021-09-27 14:03:07 +080069};
70
developer565bacb2021-09-28 21:26:32 +080071&watchdog {
72 status = "okay";
developer691e73f2021-06-28 19:41:35 +080073};
74
developer565bacb2021-09-28 21:26:32 +080075&eth {
76 status = "okay";
77
78 gmac0: mac@0 {
79 compatible = "mediatek,eth-mac";
80 reg = <0>;
81 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080082
83 fixed-link {
84 speed = <2500>;
85 full-duplex;
86 pause;
developer8b1069e2022-08-26 17:49:39 +080087 link-gpio = <&pio 47 0>;
88 phy-handle = <&phy5>;
89 label = "lan5";
developer283fc452022-08-18 19:50:33 +080090 };
developer565bacb2021-09-28 21:26:32 +080091 };
92
93 gmac1: mac@1 {
94 compatible = "mediatek,eth-mac";
95 reg = <1>;
96 phy-mode = "2500base-x";
developer8b1069e2022-08-26 17:49:39 +080097
98 fixed-link {
99 speed = <2500>;
100 full-duplex;
101 pause;
102 link-gpio = <&pio 46 0>;
103 phy-handle = <&phy6>;
104 };
developer565bacb2021-09-28 21:26:32 +0800105 };
106
107 mdio: mdio-bus {
108 #address-cells = <1>;
109 #size-cells = <0>;
developer691e73f2021-06-28 19:41:35 +0800110
developerf0a1e452022-08-15 12:06:11 +0800111 reset-gpios = <&pio 6 1>;
112 reset-delay-us = <600>;
113
developer565bacb2021-09-28 21:26:32 +0800114 phy5: phy@5 {
developer8b1069e2022-08-26 17:49:39 +0800115 compatible = "ethernet-phy-id67c9.de0a";
developer565bacb2021-09-28 21:26:32 +0800116 reg = <5>;
developer565bacb2021-09-28 21:26:32 +0800117 };
developer691e73f2021-06-28 19:41:35 +0800118
developer565bacb2021-09-28 21:26:32 +0800119 phy6: phy@6 {
developer8b1069e2022-08-26 17:49:39 +0800120 compatible = "ethernet-phy-id67c9.de0a";
developer565bacb2021-09-28 21:26:32 +0800121 reg = <6>;
developer565bacb2021-09-28 21:26:32 +0800122 };
123
124 switch@0 {
125 compatible = "mediatek,mt7531";
126 reg = <31>;
127 reset-gpios = <&pio 5 0>;
128
129 ports {
130 #address-cells = <1>;
131 #size-cells = <0>;
132
133 port@0 {
134 reg = <0>;
135 label = "lan0";
136 };
137
138 port@1 {
139 reg = <1>;
140 label = "lan1";
141 };
142
143 port@2 {
144 reg = <2>;
145 label = "lan2";
146 };
147
148 port@3 {
149 reg = <3>;
150 label = "lan3";
151 };
152
153 port@4 {
154 reg = <4>;
155 label = "lan4";
156 };
157
158 port@5 {
159 reg = <5>;
160 label = "lan5";
161 phy-mode = "2500base-x";
developer8b1069e2022-08-26 17:49:39 +0800162
163 fixed-link {
164 speed = <2500>;
165 full-duplex;
166 pause;
167 };
developer565bacb2021-09-28 21:26:32 +0800168 };
169
170 port@6 {
171 reg = <6>;
172 label = "cpu";
173 ethernet = <&gmac0>;
174 phy-mode = "2500base-x";
175
176 fixed-link {
177 speed = <2500>;
178 full-duplex;
179 pause;
180 };
developer691e73f2021-06-28 19:41:35 +0800181 };
182 };
183 };
184 };
185};
developer565bacb2021-09-28 21:26:32 +0800186
187&hnat {
188 mtketh-wan = "eth1";
189 mtketh-lan = "lan";
190 mtketh-max-gmac = <2>;
191 status = "okay";
192};
193
194&spi0 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&spi_flash_pins>;
197 cs-gpios = <0>, <0>;
198 status = "okay";
199 spi_nor@0 {
200 #address-cells = <1>;
201 #size-cells = <1>;
202 compatible = "jedec,spi-nor";
203 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800204 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800205 spi-tx-buswidth = <4>;
206 spi-rx-buswidth = <4>;
207 };
208};
209
210&spi1 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&spic_pins_g2>;
213 status = "okay";
214};
215
216&pcie0 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pcie0_pins>;
219 status = "okay";
220};
221
222&wbsys {
223 mediatek,mtd-eeprom = <&factory 0x0000>;
224 status = "okay";
225};
226
227&pio {
228 spi_flash_pins: spi-flash-pins-33-to-38 {
229 mux {
230 function = "flash";
231 groups = "spi0", "spi0_wp_hold";
232 };
233 conf-pu {
234 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
235 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800236 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800237 };
238 conf-pd {
239 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
240 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800241 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800242 };
243 };
244};