blob: f7de3dd71d97815db4fe8f696ebf219ee4299140 [file] [log] [blame]
developer691e73f2021-06-28 19:41:35 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developer691e73f2021-06-28 19:41:35 +08005/ {
6 model = "MediaTek MT7986a RFB";
7 compatible = "mediatek,mt7986a-2500wan-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 sound {
18 compatible = "mediatek,mt7986-wm8960-machine";
19 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developer691e73f2021-06-28 19:41:35 +080027};
28
developer209e52d2022-06-30 11:32:57 +080029&fan {
30 pwms = <&pwm 1 50000 0>;
31 status = "disabled";
32};
33
developer565bacb2021-09-28 21:26:32 +080034&pwm {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
developer691e73f2021-06-28 19:41:35 +080037 status = "okay";
developer565bacb2021-09-28 21:26:32 +080038};
developer5b91be72021-09-27 14:03:07 +080039
developer565bacb2021-09-28 21:26:32 +080040&uart0 {
41 status = "okay";
42};
43
44&uart1 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&uart1_pins>;
47 status = "okay";
48};
49
50&uart2 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&uart2_pins>;
53 status = "okay";
54};
55
56&i2c0 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&i2c_pins>;
59 status = "okay";
60
61 wm8960: wm8960@1a {
62 compatible = "wlf,wm8960";
63 reg = <0x1a>;
developer5b91be72021-09-27 14:03:07 +080064 };
65};
66
developer565bacb2021-09-28 21:26:32 +080067&auxadc {
68 status = "okay";
developer5b91be72021-09-27 14:03:07 +080069};
70
developer565bacb2021-09-28 21:26:32 +080071&watchdog {
72 status = "okay";
developer691e73f2021-06-28 19:41:35 +080073};
74
developer565bacb2021-09-28 21:26:32 +080075&eth {
76 status = "okay";
77
78 gmac0: mac@0 {
79 compatible = "mediatek,eth-mac";
80 reg = <0>;
81 phy-mode = "2500base-x";
82
83 fixed-link {
84 speed = <2500>;
85 full-duplex;
86 pause;
87 };
88 };
89
90 gmac1: mac@1 {
91 compatible = "mediatek,eth-mac";
92 reg = <1>;
93 phy-mode = "2500base-x";
94
95 fixed-link {
96 speed = <2500>;
97 full-duplex;
98 pause;
99 };
100 };
101
102 mdio: mdio-bus {
103 #address-cells = <1>;
104 #size-cells = <0>;
developer691e73f2021-06-28 19:41:35 +0800105
developer565bacb2021-09-28 21:26:32 +0800106 phy5: phy@5 {
107 compatible = "ethernet-phy-id67c9.de0a";
108 reg = <5>;
109 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800110 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800111 reset-deassert-us = <20000>;
112 phy-mode = "2500base-x";
113 };
developer691e73f2021-06-28 19:41:35 +0800114
developer565bacb2021-09-28 21:26:32 +0800115 phy6: phy@6 {
116 compatible = "ethernet-phy-id67c9.de0a";
117 reg = <6>;
118 phy-mode = "2500base-x";
119 };
120
121 switch@0 {
122 compatible = "mediatek,mt7531";
123 reg = <31>;
124 reset-gpios = <&pio 5 0>;
125
126 ports {
127 #address-cells = <1>;
128 #size-cells = <0>;
129
130 port@0 {
131 reg = <0>;
132 label = "lan0";
133 };
134
135 port@1 {
136 reg = <1>;
137 label = "lan1";
138 };
139
140 port@2 {
141 reg = <2>;
142 label = "lan2";
143 };
144
145 port@3 {
146 reg = <3>;
147 label = "lan3";
148 };
149
150 port@4 {
151 reg = <4>;
152 label = "lan4";
153 };
154
155 port@5 {
156 reg = <5>;
157 label = "lan5";
158 phy-mode = "2500base-x";
159
160 fixed-link {
161 speed = <2500>;
162 full-duplex;
163 pause;
164 };
165 };
166
167 port@6 {
168 reg = <6>;
169 label = "cpu";
170 ethernet = <&gmac0>;
171 phy-mode = "2500base-x";
172
173 fixed-link {
174 speed = <2500>;
175 full-duplex;
176 pause;
177 };
developer691e73f2021-06-28 19:41:35 +0800178 };
179 };
180 };
181 };
182};
developer565bacb2021-09-28 21:26:32 +0800183
184&hnat {
185 mtketh-wan = "eth1";
186 mtketh-lan = "lan";
187 mtketh-max-gmac = <2>;
188 status = "okay";
189};
190
191&spi0 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&spi_flash_pins>;
194 cs-gpios = <0>, <0>;
195 status = "okay";
196 spi_nor@0 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 compatible = "jedec,spi-nor";
200 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800201 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800202 spi-tx-buswidth = <4>;
203 spi-rx-buswidth = <4>;
204 };
205};
206
207&spi1 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&spic_pins_g2>;
210 status = "okay";
211};
212
213&pcie0 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pcie0_pins>;
216 status = "okay";
217};
218
219&wbsys {
220 mediatek,mtd-eeprom = <&factory 0x0000>;
221 status = "okay";
222};
223
224&pio {
225 spi_flash_pins: spi-flash-pins-33-to-38 {
226 mux {
227 function = "flash";
228 groups = "spi0", "spi0_wp_hold";
229 };
230 conf-pu {
231 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
232 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800233 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800234 };
235 conf-pd {
236 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
237 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800238 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800239 };
240 };
241};