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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 2b101966085d8aa72734643c4045a77ee1b9d1ae / . / target / linux / mediatek / files-5.4 / drivers / clk / mediatek / clk-mt7988.c
blob: 93585cec295af5777e1f03fff18ec30ae6b2cd94 [file] [log] [blame]
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1/*
2 * Copyright (c) 2022 MediaTek Inc.
3 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/mfd/syscon.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/mfd/syscon.h>
24
25#include "clk-mtk.h"
26#include "clk-gate.h"
27#include "clk-mux.h"
28
29#include <dt-bindings/clock/mt7988-clk.h>
30
31static DEFINE_SPINLOCK(mt7988_clk_lock);
32
33static const struct mtk_fixed_factor top_divs[] __initconst = {
34 FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
35 FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
36 FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
37 FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
38 FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
39 FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
40 FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
41 FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
42 FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
43 FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
44 FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
45 FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
46 FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
47 FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
48 FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", "apll2", 1, 4),
49 FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
50 FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
51 FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
52 FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
53 FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
54 FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
55 FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
56 FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", "net1pll", 1, 64),
57 FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", "net1pll", 1, 128),
58 FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
59 FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
60 FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
61 FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
62 FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", "net2pll", 1, 32),
63 FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
64 FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", "net2pll", 1, 8),
65 FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
66 FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
67 FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", "netsyspll", 1, 1),
68 FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", "msdcpll", 1, 1),
69 FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
70 FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
71 FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
72 FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", "cb_rtc_32p7k", 1, 1),
73 FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", "clkxtal", 1, 1),
74 FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
75 FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", "netsys_gsw_sel", 1, 1),
76 FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
77 FACTOR(CK_TOP_EIP197, "eip197", "eip197_sel", 1, 1),
78 FACTOR(CK_TOP_EMMC_250M, "emmc_250m", "emmc_250m_sel", 1, 1),
79 FACTOR(CK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
80 FACTOR(CK_TOP_SPI, "spi", "spi_sel", 1, 1),
81 FACTOR(CK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
82 FACTOR(CK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
83 FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
84 FACTOR(CK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
85 FACTOR(CK_TOP_USB_SYS, "usb_sys", "usb_sys_sel", 1, 1),
86 FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", "usb_sys_p1_sel", 1, 1),
87 FACTOR(CK_TOP_USB_XHCI, "usb_xhci", "usb_xhci_sel", 1, 1),
88 FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", "usb_xhci_p1_sel", 1, 1),
89 FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
90 FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", "usb_frmcnt_p1_sel", 1,
91 1),
92 FACTOR(CK_TOP_AUD, "aud", "aud_sel", 1, 1),
93 FACTOR(CK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
94 FACTOR(CK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
95 FACTOR(CK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
96 FACTOR(CK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
97 FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", "csw_infra_f26m_sel", 1, 1),
98 FACTOR(CK_TOP_USB_REF, "usb_ref", "cksq_src", 1, 1),
99 FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", "cksq_src", 1, 1),
100};
101
102static const struct mtk_fixed_factor infra_divs[] __initconst = {
103 FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", "csw_infra_f26m_sel", 1, 1),
104 FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", "pwm_sel", 1, 1),
105 FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", "pextp_tl_ck_sel",
106 1, 1),
107 FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
108 "pextp_tl_ck_p1_sel", 1, 1),
109 FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
110 "pextp_tl_ck_p2_sel", 1, 1),
111 FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
112 "pextp_tl_ck_p3_sel", 1, 1),
113 FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1),
114 FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", "infra_133m_hck", 1, 1),
115 FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1),
116 FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", "aud_l", 1, 1),
117 FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", "a1sys", 1, 1),
118 FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", "a_tuner", 1, 1),
119 FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", "i2c_bck", 1, 1),
120 FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", "uart_sel", 1, 1),
121 FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", "uart_sel", 1, 1),
122 FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", "uart_sel", 1, 1),
123 FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", "nfi1x", 1, 1),
124 FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", "spinfi_bck", 1, 1),
125 FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", "spi", 1, 1),
126 FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", "spim_mst", 1, 1),
127 FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", "infra_frtc", 1, 1),
128 FACTOR(CK_INFRA_FRTC, "infra_frtc", "cb_rtc_32k", 1, 1),
129 FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", "emmc_400m", 1, 1),
130 FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", "emmc_250m", 1,
131 1),
132 FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1),
133 FACTOR(CK_INFRA_USB_O, "infra_usb_o", "usb_ref", 1, 1),
134 FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", "usb_ck_p1", 1, 1),
135 FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", "usb_frmcnt", 1, 1),
136 FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
137 "usb_frmcnt_p1", 1, 1),
138 FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", "usb_xhci", 1, 1),
139 FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", "usb_xhci_p1", 1,
140 1),
141 FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "clkxtal", 1, 1),
142 FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "clkxtal", 1, 1),
143 FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", "clkxtal", 1, 1),
144 FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", "clkxtal", 1, 1),
145 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
146 "clkxtal", 1, 1),
147 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
148 "clkxtal", 1, 1),
149 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
150 "clkxtal", 1, 1),
151 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
152 "clkxtal", 1, 1),
153 FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", "csw_infra_f26m", 1, 1),
154 FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", "csw_infra_f26m", 1, 1),
155 FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", "sysaxi", 1, 1),
156 FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi", 1, 1),
157 FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", "sysaxi", 1, 1),
158 FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", "usb_sys", 1, 1),
159 FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", "usb_sys_p1", 1, 1),
160};
161
162static const char *const mcu_bus_div_parents[] = { "cb_cksq_40m", "ccipll2_b",
163 "cb_net1_d4" };
164
165static const char *const mcu_arm_div_parents[] = { "cb_cksq_40m", "arm_b",
166 "cb_net1_d4" };
167
168static struct mtk_composite mcu_muxes[] = {
169 /* bus_pll_divider_cfg */
170 MUX_GATE_FLAGS(CK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
171 mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
172 /* mp2_pll_divider_cfg */
173 MUX_GATE_FLAGS(CK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
174 mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
175};
176
177static const char *const netsys_parents[] = { "cb_cksq_40m", "cb_net2_d2",
178 "cb_mm_d2" };
179
180static const char *const netsys_500m_parents[] = { "cb_cksq_40m", "cb_net1_d5",
181 "net1_d5_d2" };
182
183static const char *const netsys_2x_parents[] = { "cb_cksq_40m", "cb_net2_800m",
184 "cb_mm_720m" };
185
186static const char *const netsys_gsw_parents[] = { "cb_cksq_40m", "cb_net1_d4",
187 "cb_net1_d5" };
188
189static const char *const eth_gmii_parents[] = { "cb_cksq_40m", "net1_d5_d4" };
190
191static const char *const netsys_mcu_parents[] = { "cb_cksq_40m", "cb_net2_800m",
192 "cb_mm_720m", "cb_net1_d4",
193 "cb_net1_d5", "cb_m_416m" };
194
195static const char *const eip197_parents[] = { "cb_cksq_40m", "cb_netsys_850m",
196 "cb_net2_800m", "cb_mm_720m",
197 "cb_net1_d4", "cb_net1_d5" };
198
199static const char *const axi_infra_parents[] = { "cb_cksq_40m", "net1_d8_d2" };
200
201static const char *const uart_parents[] = { "cb_cksq_40m", "cb_m_d8",
202 "m_d8_d2" };
203
204static const char *const emmc_250m_parents[] = { "cb_cksq_40m", "net1_d5_d2",
205 "cb_mm_d4" };
206
207static const char *const emmc_400m_parents[] = { "cb_cksq_40m", "cb_msdc_400m",
208 "cb_mm_d2", "cb_m_d2",
209 "cb_mm_d4", "net1_d8_d2" };
210
211static const char *const spi_parents[] = { "cb_cksq_40m", "cb_m_d2",
212 "cb_mm_d4", "net1_d8_d2",
213 "cb_net2_d6", "net1_d5_d4",
214 "cb_m_d4", "net1_d8_d4" };
215
216static const char *const nfi1x_parents[] = { "cb_cksq_40m", "cb_mm_d4",
217 "net1_d8_d2", "cb_net2_d6",
218 "cb_m_d4", "cb_mm_d8",
219 "net1_d8_d4", "cb_m_d8" };
220
221static const char *const spinfi_parents[] = { "cksq_40m_d2", "cb_cksq_40m",
222 "net1_d5_d4", "cb_m_d4",
223 "cb_mm_d8", "net1_d8_d4",
224 "mm_d6_d2", "cb_m_d8" };
225
226static const char *const pwm_parents[] = { "cb_cksq_40m", "net1_d8_d2",
227 "net1_d5_d4", "cb_m_d4",
228 "m_d8_d2", "cb_rtc_32k" };
229
230static const char *const i2c_parents[] = { "cb_cksq_40m", "net1_d5_d4",
231 "cb_m_d4", "net1_d8_d4" };
232
233static const char *const pcie_mbist_250m_parents[] = { "cb_cksq_40m",
234 "net1_d5_d2" };
235
236static const char *const pextp_tl_ck_parents[] = { "cb_cksq_40m", "cb_net2_d6",
237 "cb_mm_d8", "m_d8_d2",
238 "cb_rtc_32k" };
239
240static const char *const usb_frmcnt_parents[] = { "cb_cksq_40m",
241 "cb_mm_d3_d5" };
242
243static const char *const aud_parents[] = { "cb_cksq_40m", "cb_apll2_196m" };
244
245static const char *const a1sys_parents[] = { "cb_cksq_40m", "cb_apll2_d4" };
246
247static const char *const aud_l_parents[] = { "cb_cksq_40m", "cb_apll2_196m",
248 "m_d8_d2" };
249
250static const char *const sspxtp_parents[] = { "cksq_40m_d2", "m_d8_d2" };
251
252static const char *const usxgmii_sbus_0_parents[] = { "cb_cksq_40m",
253 "net1_d8_d4" };
254
255static const char *const sgm_0_parents[] = { "cb_cksq_40m", "cb_sgm_325m" };
256
257static const char *const sysapb_parents[] = { "cb_cksq_40m", "m_d3_d2" };
258
259static const char *const eth_refck_50m_parents[] = { "cb_cksq_40m",
260 "net2_d4_d4" };
261
262static const char *const eth_sys_200m_parents[] = { "cb_cksq_40m",
263 "cb_net2_d4" };
264
265static const char *const eth_xgmii_parents[] = { "cksq_40m_d2", "net1_d8_d8",
266 "net1_d8_d16" };
267
268static const char *const bus_tops_parents[] = { "cb_cksq_40m", "cb_net1_d5",
269 "cb_net2_d2" };
270
271static const char *const npu_tops_parents[] = { "cb_cksq_40m", "cb_net2_800m" };
272
273static const char *const dramc_md32_parents[] = { "cb_cksq_40m", "cb_m_d2",
274 "cb_wedmcu_208m" };
275
276static const char *const da_xtp_glb_p0_parents[] = { "cb_cksq_40m",
277 "cb_net2_d8" };
278
279static const char *const mcusys_backup_625m_parents[] = { "cb_cksq_40m",
280 "cb_net1_d4" };
281
282static const char *const macsec_parents[] = { "cb_cksq_40m", "cb_sgm_325m",
283 "cb_net1_d8" };
284
285static const char *const netsys_tops_400m_parents[] = { "cb_cksq_40m",
286 "cb_net2_d2" };
287
288static const char *const eth_mii_parents[] = { "cksq_40m_d2", "net2_d4_d8" };
289
290static struct mtk_mux top_muxes[] = {
291 /* CLK_CFG_0 */
292 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
293 0x000, 0x004, 0x008, 0, 2, 7, 0x1C0, 0),
294 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
295 netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15,
296 0x1C0, 1),
297 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
298 netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
299 0x1C0, 2),
300 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
301 netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, 31,
302 0x1C0, 3),
303 /* CLK_CFG_1 */
304 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
305 eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
306 0x1C0, 4),
307 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
308 netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
309 0x1C0, 5),
310 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
311 netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, 23,
312 0x1C0, 6),
313 MUX_GATE_CLR_SET_UPD(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
314 0x010, 0x014, 0x018, 24, 3, 31, 0x1C0, 7),
315 /* CLK_CFG_2 */
316 MUX_GATE_CLR_SET_UPD(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
317 axi_infra_parents, 0x020, 0x024, 0x028, 0, 1, 7,
318 0x1C0, 8),
319 MUX_GATE_CLR_SET_UPD(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
320 0x024, 0x028, 8, 2, 15, 0x1C0, 9),
321 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
322 emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
323 0x1C0, 10),
324 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
325 emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
326 0x1C0, 11),
327 /* CLK_CFG_3 */
328 MUX_GATE_CLR_SET_UPD(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
329 0x034, 0x038, 0, 3, 7, 0x1C0, 12),
330 MUX_GATE_CLR_SET_UPD(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
331 0x030, 0x034, 0x038, 8, 3, 15, 0x1C0, 13),
332 MUX_GATE_CLR_SET_UPD(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
333 0x030, 0x034, 0x038, 16, 3, 23, 0x1C0, 14),
334 MUX_GATE_CLR_SET_UPD(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
335 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15),
336 /* CLK_CFG_4 */
337 MUX_GATE_CLR_SET_UPD(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
338 0x044, 0x048, 0, 3, 7, 0x1C0, 16),
339 MUX_GATE_CLR_SET_UPD(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
340 0x044, 0x048, 8, 2, 15, 0x1C0, 17),
341 MUX_GATE_CLR_SET_UPD(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
342 pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16,
343 1, 23, 0x1C0, 18),
344 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
345 pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
346 31, 0x1C0, 19),
347 /* CLK_CFG_5 */
348 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
349 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
350 0x1C0, 20),
351 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
352 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, 15,
353 0x1C0, 21),
354 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
355 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
356 23, 0x1C0, 22),
357 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_SYS_SEL, "usb_sys_sel",
358 eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
359 0x1C0, 23),
360 /* CLK_CFG_6 */
361 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
362 eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
363 0x1C0, 24),
364 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
365 eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
366 0x1C0, 25),
367 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
368 eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
369 0x1C0, 26),
370 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
371 usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, 31,
372 0x1C0, 27),
373 /* CLK_CFG_7 */
374 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
375 usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
376 0x1C0, 28),
377 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
378 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
379 MUX_GATE_CLR_SET_UPD(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
380 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30),
381 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
382 0x070, 0x074, 0x078, 24, 2, 31, 0x1C4, 0),
383 /* CLK_CFG_8 */
384 MUX_GATE_CLR_SET_UPD(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
385 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
386 MUX_GATE_CLR_SET_UPD(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
387 0x080, 0x084, 0x088, 8, 1, 15, 0x1C4, 2),
388 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents,
389 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
390 MUX_GATE_CLR_SET_UPD(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
391 usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1,
392 31, 0x1C4, 4),
393 /* CLK_CFG_9 */
394 MUX_GATE_CLR_SET_UPD(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
395 usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
396 7, 0x1C4, 5),
397 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
398 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]399 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
400 usxgmii_sbus_0_parents,
401 0x090, 0x094, 0x098, 16, 1,
402 23, 0x1C4, 7, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]403 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
404 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8),
405 /* CLK_CFG_10 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]406 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
407 usxgmii_sbus_0_parents,
408 0x0A0, 0x0A4, 0x0A8, 0, 1,
409 7, 0x1C4, 9, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]410 MUX_GATE_CLR_SET_UPD(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
411 sspxtp_parents, 0x0A0, 0x0A4, 0x0A8, 8, 1, 15,
412 0x1C4, 10),
413 MUX_GATE_CLR_SET_UPD(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
414 sspxtp_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23,
415 0x1C4, 11),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]416 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAXI_SEL, "sysaxi_sel",
417 axi_infra_parents,
418 0x0A0, 0x0A4, 0x0A8, 24, 1, 31,
419 0x1C4, 12, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]420 /* CLK_CFG_11 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]421 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAPB_SEL, "sysapb_sel",
422 sysapb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 1, 7,
423 0x1C4, 13, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]424 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
425 eth_refck_50m_parents, 0x0B0, 0x0B4, 0x0B8, 8, 1,
426 15, 0x1C4, 14),
427 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
428 eth_sys_200m_parents, 0x0B0, 0x0B4, 0x0B8, 16, 1,
429 23, 0x1C4, 15),
430 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_SEL, "eth_sys_sel",
431 pcie_mbist_250m_parents, 0x0B0, 0x0B4, 0x0B8, 24,
432 1, 31, 0x1C4, 16),
433 /* CLK_CFG_12 */
434 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
435 eth_xgmii_parents, 0x0C0, 0x0C4, 0x0C8, 0, 2, 7,
436 0x1C4, 17),
437 MUX_GATE_CLR_SET_UPD(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
438 bus_tops_parents, 0x0C0, 0x0C4, 0x0C8, 8, 2, 15,
439 0x1C4, 18),
440 MUX_GATE_CLR_SET_UPD(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
441 npu_tops_parents, 0x0C0, 0x0C4, 0x0C8, 16, 1, 23,
442 0x1C4, 19),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]443 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_SEL, "dramc_sel",
444 sspxtp_parents, 0x0C0, 0x0C4, 0x0C8, 24, 1, 31,
445 0x1C4, 20, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]446 /* CLK_CFG_13 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]447 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
448 dramc_md32_parents,
449 0x0D0, 0x0D4, 0x0D8, 0, 2, 7,
450 0x1C4, 21, CLK_IS_CRITICAL),
451 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel",
452 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 8, 1, 15,
453 0x1C4, 22, CLK_IS_CRITICAL),
454 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
455 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 16, 1, 23,
456 0x1C4, 23, CLK_IS_CRITICAL),
457 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
458 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 24, 1, 31,
459 0x1C4, 24, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]460 /* CLK_CFG_14 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]461 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
462 sspxtp_parents, 0x0E0, 0x0E4, 0x0E8, 0, 1, 7,
463 0x1C4, 25, CLK_IS_CRITICAL),
464 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
465 sspxtp_parents, 0x0E0, 0x0E4, 0x0E8, 8, 1, 15,
466 0x1C4, 26, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]467 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
468 da_xtp_glb_p0_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1,
469 23, 0x1C4, 27),
470 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
471 da_xtp_glb_p0_parents, 0x0E0, 0x0E4, 0x0E8, 24, 1,
472 31, 0x1C4, 28),
473 /* CLK_CFG_15 */
474 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
475 da_xtp_glb_p0_parents, 0x0F0, 0x0F4, 0x0F8, 0, 1,
476 7, 0x1C4, 29),
477 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
478 da_xtp_glb_p0_parents, 0x0F0, 0x0F4, 0x0F8, 8, 1,
479 15, 0x1C4, 30),
480 MUX_GATE_CLR_SET_UPD(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
481 0x0F4, 0x0F8, 16, 1, 23, 0x1C8, 0),
482 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel",
483 sspxtp_parents, 0x0F0, 0x0F4, 0x0F8, 24, 1, 31,
484 0x1C8, 1),
485 /* CLK_CFG_16 */
486 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
487 0x0100, 0x104, 0x108, 0, 1, 7, 0x1C8, 2),
488 MUX_GATE_CLR_SET_UPD(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
489 sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
490 0x1C8, 3),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]491 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_MCUSYS_BACKUP_625M_SEL,
492 "mcusys_backup_625m_sel",
493 mcusys_backup_625m_parents,
494 0x0100, 0x104, 0x108,
495 16, 1, 23, 0x1C8, 4, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]496 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SYNC_250M_SEL,
497 "netsys_sync_250m_sel", pcie_mbist_250m_parents,
498 0x0100, 0x104, 0x108, 24, 1, 31, 0x1C8, 5),
499 /* CLK_CFG_17 */
500 MUX_GATE_CLR_SET_UPD(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
501 0x0110, 0x114, 0x118, 0, 2, 7, 0x1C8, 6),
502 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_TOPS_400M_SEL,
503 "netsys_tops_400m_sel", netsys_tops_400m_parents,
504 0x0110, 0x114, 0x118, 8, 1, 15, 0x1C8, 7),
505 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_PPEFB_250M_SEL,
506 "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
507 0x0110, 0x114, 0x118, 16, 1, 23, 0x1C8, 8),
508 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
509 netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
510 0x1C8, 9),
511 /* CLK_CFG_18 */
512 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents,
513 0x0120, 0x124, 0x128, 0, 1, 7, 0x1C8, 10),
514 MUX_GATE_CLR_SET_UPD(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL,
515 "ck_npu_sel_cm_tops_sel", netsys_2x_parents,
516 0x0120, 0x124, 0x128, 8, 2, 15, 0x1C8, 11),
517};
518
519static const char *const infra_mux_uart0_parents[] __initconst = {
520 "infra_ck_f26m", "infra_uart_o0"
521};
522
523static const char *const infra_mux_uart1_parents[] __initconst = {
524 "infra_ck_f26m", "infra_uart_o1"
525};
526
527static const char *const infra_mux_uart2_parents[] __initconst = {
528 "infra_ck_f26m", "infra_uart_o2"
529};
530
531static const char *const infra_mux_spi0_parents[] __initconst = {
532 "infra_i2c_o", "infra_spi0_o"
533};
534
535static const char *const infra_mux_spi1_parents[] __initconst = {
536 "infra_i2c_o", "infra_spi1_o"
537};
538
539static const char *const infra_pwm_bck_parents[] __initconst = {
540 "csw_infra_f32k", "infra_ck_f26m", "infra_66m_mck", "infra_pwm_o"
541};
542
543static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
544 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
545 "infra_pcie_ck_occ_p0"
546};
547
548static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
549 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
550 "infra_pcie_ck_occ_p1"
551};
552
553static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
554 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
555 "infra_pcie_ck_occ_p2"
556};
557
558static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
559 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
560 "infra_pcie_ck_occ_p3"
561};
562
563static const struct mtk_mux infra_muxes[] = {
564 /* MODULE_CLK_SEL_0 */
565 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
566 infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0,
567 1, -1, -1, -1),
568 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
569 infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1,
570 1, -1, -1, -1),
571 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
572 infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2,
573 1, -1, -1, -1),
574 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
575 infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
576 1, -1, -1, -1),
577 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
578 infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
579 1, -1, -1, -1),
580 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
581 infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
582 1, -1, -1, -1),
583 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_SEL, "infra_pwm_sel",
584 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
585 2, -1, -1, -1),
586 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
587 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
588 2, -1, -1, -1),
589 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
590 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
591 2, -1, -1, -1),
592 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
593 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
594 2, -1, -1, -1),
595 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
596 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
597 2, -1, -1, -1),
598 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
599 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
600 2, -1, -1, -1),
601 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
602 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
603 2, -1, -1, -1),
604 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
605 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
606 2, -1, -1, -1),
607 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
608 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
609 2, -1, -1, -1),
610 /* MODULE_CLK_SEL_1 */
611 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
612 "infra_pcie_gfmux_tl_o_p0_sel",
613 infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
614 0x0020, 0x0024, 0, 2, -1, -1, -1),
615 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
616 "infra_pcie_gfmux_tl_o_p1_sel",
617 infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
618 0x0020, 0x0024, 2, 2, -1, -1, -1),
619 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
620 "infra_pcie_gfmux_tl_o_p2_sel",
621 infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
622 0x0020, 0x0024, 4, 2, -1, -1, -1),
623 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
624 "infra_pcie_gfmux_tl_o_p3_sel",
625 infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
626 0x0020, 0x0024, 6, 2, -1, -1, -1),
627};
628
developer4323f7e2022-10-13 11:09:46 +0800[diff] [blame]629static struct mtk_composite top_aud_divs[] = {
630 DIV_GATE(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
631 0x0420, 0, 0x0420, 8, 8),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]632};
633
634static const struct mtk_gate_regs infra0_cg_regs = {
635 .set_ofs = 0x10,
636 .clr_ofs = 0x14,
637 .sta_ofs = 0x18,
638};
639
640static const struct mtk_gate_regs infra1_cg_regs = {
641 .set_ofs = 0x40,
642 .clr_ofs = 0x44,
643 .sta_ofs = 0x48,
644};
645
646static const struct mtk_gate_regs infra2_cg_regs = {
647 .set_ofs = 0x50,
648 .clr_ofs = 0x54,
649 .sta_ofs = 0x58,
650};
651
652static const struct mtk_gate_regs infra3_cg_regs = {
653 .set_ofs = 0x60,
654 .clr_ofs = 0x64,
655 .sta_ofs = 0x68,
656};
657
658#define GATE_INFRA0(_id, _name, _parent, _shift) \
659 { \
660 .id = _id, .name = _name, .parent_name = _parent, \
661 .regs = &infra0_cg_regs, .shift = _shift, \
662 .ops = &mtk_clk_gate_ops_setclr, \
663 }
664
665#define GATE_INFRA1(_id, _name, _parent, _shift) \
666 { \
667 .id = _id, .name = _name, .parent_name = _parent, \
668 .regs = &infra1_cg_regs, .shift = _shift, \
669 .ops = &mtk_clk_gate_ops_setclr, \
670 }
671
672#define GATE_INFRA2(_id, _name, _parent, _shift) \
673 { \
674 .id = _id, .name = _name, .parent_name = _parent, \
675 .regs = &infra2_cg_regs, .shift = _shift, \
676 .ops = &mtk_clk_gate_ops_setclr, \
677 }
678
679#define GATE_INFRA3(_id, _name, _parent, _shift) \
680 { \
681 .id = _id, .name = _name, .parent_name = _parent, \
682 .regs = &infra3_cg_regs, .shift = _shift, \
683 .ops = &mtk_clk_gate_ops_setclr, \
684 }
685
developeref309762023-01-11 15:53:46 +0800[diff] [blame]686#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \
687 .id = _id, .name = _name, .parent_name = _parent, \
688 .regs = _regs, .shift = _shift, \
689 .flags = CLK_IS_CRITICAL, \
690 .ops = &mtk_clk_gate_ops_setclr, \
691 }
692
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]693static const struct mtk_gate infra_clks[] __initconst = {
694 /* INFRA0 */
695 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
696 "infra_pcie_peri_ck_26m_ck_p0", "infra_f26m_o0", 7),
697 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
698 "infra_pcie_peri_ck_26m_ck_p1", "infra_f26m_o0", 8),
699 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
700 "infra_pcie_peri_ck_26m_ck_p2", "infra_f26m_o0", 9),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]701 GATE_CRITICAL(CK_INFRA_PCIE_PERI_26M_CK_P3,
702 "infra_pcie_peri_ck_26m_ck_p3", "infra_f26m_o0",
703 &infra0_cg_regs, 10),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]704 /* INFRA1 */
705 GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
706 "infra_66m_mck", 0),
707 GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
708 "infra_66m_mck", 1),
709 GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
710 "infra_pwm_sel", 2),
711 GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
712 "infra_pwm_ck1_sel", 3),
713 GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
714 "infra_pwm_ck2_sel", 4),
715 GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
716 "infra_pwm_ck3_sel", 5),
717 GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
718 "infra_pwm_ck4_sel", 6),
719 GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
720 "infra_pwm_ck5_sel", 7),
721 GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
722 "infra_pwm_ck6_sel", 8),
723 GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
724 "infra_pwm_ck7_sel", 9),
725 GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
726 "infra_pwm_ck8_sel", 10),
727 GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
728 "infra_133m_mck", 12),
729 GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
730 "infra_66m_phck", 13),
731 GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", "infra_ck_f26m", 14),
732 GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", "infra_faud_l_o", 15),
733 GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", "infra_faud_aud_o",
734 16),
735 GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", "infra_faud_eg2_o",
736 18),
737 GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "infra_ck_f26m",
738 19),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]739 GATE_CRITICAL(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
740 "infra_133m_mck", &infra1_cg_regs, 20),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]741 GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
742 "infra_66m_mck", 21),
743 GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
744 "infra_66m_mck", 29),
745 GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
746 "infra_ck_f26m", 30),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]747 /* INFRA2 */
748 GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
749 "infra_ck_f26m", 0),
750 GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", "infra_i2c_o", 1),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]751 GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
752 "infra_mux_uart0_sel", 3),
753 GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
754 "infra_mux_uart1_sel", 4),
755 GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
756 "infra_mux_uart2_sel", 5),
757 GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", "infra_nfi_o", 9),
758 GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", "infra_spinfi_o", 10),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]759 GATE_CRITICAL(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
760 "infra_66m_mck", &infra2_cg_regs, 11),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]761 GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
762 "infra_mux_spi0_sel", 12),
763 GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
764 "infra_mux_spi1_sel", 13),
765 GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
766 "infra_mux_spi2_sel", 14),
767 GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
768 "infra_66m_mck", 15),
769 GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
770 "infra_66m_mck", 16),
771 GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
772 "infra_66m_mck", 17),
773 GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
774 "infra_66m_mck", 18),
developera079b6a2023-02-22 14:49:06 +0800[diff] [blame]775 GATE_CRITICAL(CK_INFRA_RTC, "infra_f_frtc", "infra_lb_mux_frtc",
776 &infra2_cg_regs, 19),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]777 GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
778 "infra_f26m_o1", 20),
779 GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
780 21),
781 GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", "infra_fmsdc400_o",
782 22),
783 GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
784 "infra_fmsdc2_hck_occ", 23),
785 GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
786 "infra_peri_133m", 24),
787 GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
788 "infra_66m_phck", 25),
789 GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
790 "infra_133m_mck", 26),
791 GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "infra_nfi_o", 27),
792 GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
793 "infra_133m_mck", 29),
794 GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
795 "infra_66m_phck", 31),
796 /* INFRA3 */
797 GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
798 "infra_133m_phck", 0),
799 GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
800 "infra_133m_phck", 1),
801 GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "infra_66m_phck",
802 2),
803 GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
804 "infra_66m_phck", 3),
805 GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", "infra_usb_sys_o", 4),
806 GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
807 "infra_usb_sys_o_p1", 5),
808 GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", "infra_usb_o", 6),
809 GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "infra_usb_o_p1", 7),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]810 GATE_CRITICAL(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
811 "infra_usb_frmcnt_o", &infra3_cg_regs, 8),
812 GATE_CRITICAL(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
813 "infra_usb_frmcnt_o_p1", &infra3_cg_regs, 9),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]814 GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", "infra_usb_pipe_o",
815 10),
816 GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
817 "infra_usb_pipe_o_p1", 11),
818 GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", "infra_usb_utmi_o",
819 12),
820 GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
821 "infra_usb_utmi_o_p1", 13),
822 GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", "infra_usb_xhci_o",
823 14),
824 GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
825 "infra_usb_xhci_o_p1", 15),
826 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
827 "infra_pcie_gfmux_tl_o_p0_sel", 20),
828 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
829 "infra_pcie_gfmux_tl_o_p1_sel", 21),
830 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
831 "infra_pcie_gfmux_tl_o_p2_sel", 22),
832 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
833 "infra_pcie_gfmux_tl_o_p3_sel", 23),
834 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
835 "infra_pcie_pipe_ck_occ_p0", 24),
836 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
837 "infra_pcie_pipe_ck_occ_p1", 25),
838 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
839 "infra_pcie_pipe_ck_occ_p2", 26),
840 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
841 "infra_pcie_pipe_ck_occ_p3", 27),
842 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
843 "infra_133m_phck", 28),
844 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
845 "infra_133m_phck", 29),
846 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
847 "infra_133m_phck", 30),
848 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
849 "infra_133m_phck", 31),
850};
851
852static const struct mtk_gate_regs sgmii0_cg_regs = {
853 .set_ofs = 0xE4,
854 .clr_ofs = 0xE4,
855 .sta_ofs = 0xE4,
856};
857
858#define GATE_SGMII0(_id, _name, _parent, _shift) \
859 { \
860 .id = _id, .name = _name, .parent_name = _parent, \
861 .regs = &sgmii0_cg_regs, .shift = _shift, \
862 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
863 }
864
865static const struct mtk_gate sgmii0_clks[] __initconst = {
866 GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", "clkxtal", 2),
867 GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", "clkxtal", 3),
868};
869
870static const struct mtk_gate_regs sgmii1_cg_regs = {
871 .set_ofs = 0xE4,
872 .clr_ofs = 0xE4,
873 .sta_ofs = 0xE4,
874};
875
876#define GATE_SGMII1(_id, _name, _parent, _shift) \
877 { \
878 .id = _id, .name = _name, .parent_name = _parent, \
879 .regs = &sgmii1_cg_regs, .shift = _shift, \
880 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
881 }
882
883static const struct mtk_gate sgmii1_clks[] __initconst = {
884 GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", "clkxtal", 2),
885 GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", "clkxtal", 3),
886};
887
888static const struct mtk_gate_regs ethdma_cg_regs = {
889 .set_ofs = 0x30,
890 .clr_ofs = 0x30,
891 .sta_ofs = 0x30,
892};
893
894#define GATE_ETHDMA(_id, _name, _parent, _shift) \
895 { \
896 .id = _id, .name = _name, .parent_name = _parent, \
897 .regs = &ethdma_cg_regs, .shift = _shift, \
898 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
899 }
900
901static const struct mtk_gate ethdma_clks[] __initconst = {
902 GATE_ETHDMA(CK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "clkxtal", 0),
903 GATE_ETHDMA(CK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "clkxtal", 1),
904 GATE_ETHDMA(CK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "clkxtal", 2),
905 GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x", 6),
906 GATE_ETHDMA(CK_ETHDMA_GP2_EN, "ethdma_gp2_en", "clkxtal", 7),
907 GATE_ETHDMA(CK_ETHDMA_GP1_EN, "ethdma_gp1_en", "clkxtal", 8),
908 GATE_ETHDMA(CK_ETHDMA_GP3_EN, "ethdma_gp3_en", "clkxtal", 10),
909 GATE_ETHDMA(CK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw", 16),
910 GATE_ETHDMA(CK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197", 29),
911};
912
913static const struct mtk_gate_regs ethwarp_cg_regs = {
914 .set_ofs = 0x14,
915 .clr_ofs = 0x14,
916 .sta_ofs = 0x14,
917};
918
919#define GATE_ETHWARP(_id, _name, _parent, _shift) \
920 { \
921 .id = _id, .name = _name, .parent_name = _parent, \
922 .regs = &ethwarp_cg_regs, .shift = _shift, \
923 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
924 }
925
926static const struct mtk_gate ethwarp_clks[] __initconst = {
927 GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
928 "netsys_wed_mcu", 13),
929 GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
930 "netsys_wed_mcu", 14),
931 GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
932 "netsys_wed_mcu", 15),
933};
934
935#define MT7988_PLL_FMAX (2500UL * MHZ)
936#define MT7988_PCW_CHG_SHIFT 2
937
938#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
939 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
940 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _div_table, \
941 _parent_name) \
942 { \
943 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
944 .en_mask = _en_mask, .flags = _flags, \
945 .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
946 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
947 .tuner_reg = _tuner_reg, .tuner_en_reg = _tuner_en_reg, \
948 .tuner_en_bit = _tuner_en_bit, .pcw_reg = _pcw_reg, \
949 .pcw_shift = _pcw_shift, .pcw_chg_reg = _pcw_chg_reg, \
950 .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
951 .div_table = _div_table, .parent_name = _parent_name, \
952 }
953
954#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
955 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
956 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _parent_name) \
957 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
958 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
959 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL, \
960 _parent_name)
961
962static const struct mtk_pll_data plls[] = {
963 PLL(CK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0,
964 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104, "clkxtal"),
965 PLL(CK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
966 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114, "clkxtal"),
967 PLL(CK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR,
968 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124, "clkxtal"),
969 PLL(CK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
970 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134, "clkxtal"),
971 PLL(CK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
972 HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144,
973 "clkxtal"),
974 PLL(CK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
developeref309762023-01-11 15:53:46 +0800[diff] [blame]975 HAVE_RST_BAR | PLL_AO, 23, 32, 0x0154, 4, 0, 0, 0, 0x0158,
976 0, 0x0154, "clkxtal"),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]977 PLL(CK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0,
978 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164, "clkxtal"),
979 PLL(CK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
980 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174, "clkxtal"),
981 PLL(CK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, HAVE_RST_BAR,
982 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204, "clkxtal"),
983 PLL(CK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
984 HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214,
985 "clkxtal"),
986 PLL(CK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
987 HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304,
988 "clkxtal"),
989 PLL(CK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32,
990 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314, "clkxtal"),
991};
992
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]993static struct clk_onecell_data *mt7988_infra_clk_data __initdata;
994static struct clk_onecell_data *mt7988_infra_ao_clk_data __initdata;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]995static struct clk_onecell_data *mt7988_top_clk_data __initdata;
996static struct clk_onecell_data *mt7988_pll_clk_data __initdata;
997
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]998static void __init mtk_infracfg_init(struct device_node *node)
999{
1000 int r;
1001
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1002 mt7988_infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1003
1004 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs),
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1005 mt7988_infra_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1006
1007 r = of_clk_add_provider(node, of_clk_src_onecell_get,
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1008 mt7988_infra_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1009
1010 if (r)
1011 pr_err("%s(): could not register clock provider: %d\n",
1012 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1013}
1014CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt7988-infracfg", mtk_infracfg_init);
1015
1016static void __init mtk_topckgen_init(struct device_node *node)
1017{
1018 int r;
1019 void __iomem *base;
1020
1021 base = of_iomap(node, 0);
1022 if (!base) {
1023 pr_err("%s(): ioremap failed\n", __func__);
1024 return;
1025 }
1026
1027 mt7988_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1028
1029 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
1030 mt7988_top_clk_data);
1031 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
1032 &mt7988_clk_lock, mt7988_top_clk_data);
developer4323f7e2022-10-13 11:09:46 +0800[diff] [blame]1033 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1034 base, &mt7988_clk_lock, mt7988_top_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1035 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1036 mt7988_top_clk_data);
1037
1038 if (r)
1039 pr_err("%s(): could not register clock provider: %d\n",
1040 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1041}
1042CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7988-topckgen", mtk_topckgen_init);
1043
1044static void __init mtk_infracfg_ao_init(struct device_node *node)
1045{
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1046 int r;
1047 void __iomem *base;
1048
1049 base = of_iomap(node, 0);
1050 if (!base) {
1051 pr_err("%s(): ioremap failed\n", __func__);
1052 return;
1053 }
1054
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1055 mt7988_infra_ao_clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1056
1057 mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1058 &mt7988_clk_lock, mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1059 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1060 mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1061
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1062 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1063 mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1064
1065 if (r)
1066 pr_err("%s(): could not register clock provider: %d\n",
1067 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1068}
1069CLK_OF_DECLARE(mtk_infracfg_ao, "mediatek,mt7988-infracfg_ao",
1070 mtk_infracfg_ao_init);
1071
1072static void __init mtk_apmixedsys_init(struct device_node *node)
1073{
1074 int r;
1075
1076 mt7988_pll_clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1077
1078 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
1079 mt7988_pll_clk_data);
1080
1081 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1082 mt7988_pll_clk_data);
1083
1084 if (r)
1085 pr_err("%s(): could not register clock provider: %d\n",
1086 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1087}
1088CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7988-apmixedsys",
1089 mtk_apmixedsys_init);
1090
1091static void __init mtk_mcusys_init(struct device_node *node)
1092{
1093 struct clk_onecell_data *clk_data;
1094 int r;
1095 void __iomem *base;
1096
1097 base = of_iomap(node, 0);
1098 if (!base) {
1099 pr_err("%s(): ioremap failed\n", __func__);
1100 return;
1101 }
1102
1103 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1104 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1105 &mt7988_clk_lock, clk_data);
1106
1107 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1108
1109 if (r)
1110 pr_err("%s(): could not register clock provider: %d\n",
1111 __func__, r);
1112}
1113CLK_OF_DECLARE(mtk_mcusys, "mediatek,mt7988-mcusys", mtk_mcusys_init);
1114
1115static void __init mtk_sgmiisys_0_init(struct device_node *node)
1116{
1117 struct clk_onecell_data *clk_data;
1118 int r;
1119
1120 clk_data = mtk_alloc_clk_data(CLK_SGMII0_NR_CLK);
1121
1122 mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
1123 clk_data);
1124
1125 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1126
1127 if (r)
1128 pr_err("%s(): could not register clock provider: %d\n",
1129 __func__, r);
1130}
1131CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7988-sgmiisys_0",
1132 mtk_sgmiisys_0_init);
1133
1134static void __init mtk_sgmiisys_1_init(struct device_node *node)
1135{
1136 struct clk_onecell_data *clk_data;
1137 int r;
1138
1139 clk_data = mtk_alloc_clk_data(CLK_SGMII1_NR_CLK);
1140
1141 mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
1142 clk_data);
1143
1144 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1145
1146 if (r)
1147 pr_err("%s(): could not register clock provider: %d\n",
1148 __func__, r);
1149}
1150CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7988-sgmiisys_1",
1151 mtk_sgmiisys_1_init);
1152
1153static void __init mtk_ethdma_init(struct device_node *node)
1154{
1155 struct clk_onecell_data *clk_data;
1156 int r;
1157
1158 clk_data = mtk_alloc_clk_data(CLK_ETHDMA_NR_CLK);
1159
1160 mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
1161 clk_data);
1162
1163 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1164
1165 if (r)
1166 pr_err("%s(): could not register clock provider: %d\n",
1167 __func__, r);
1168}
1169CLK_OF_DECLARE(mtk_ethdma, "mediatek,mt7988-ethsys", mtk_ethdma_init);
1170
1171static void __init mtk_ethwarp_init(struct device_node *node)
1172{
1173 struct clk_onecell_data *clk_data;
1174 int r;
1175
1176 clk_data = mtk_alloc_clk_data(CLK_ETHWARP_NR_CLK);
1177
1178 mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
1179 clk_data);
1180
1181 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1182
1183 if (r)
1184 pr_err("%s(): could not register clock provider: %d\n",
1185 __func__, r);
1186}
1187CLK_OF_DECLARE(mtk_ethwarp, "mediatek,mt7988-ethwarp", mtk_ethwarp_init);