[][kernel][mt7988][clk][change 7988 aud clk driver]
[Description]
Change aud clk from DIV_ADJ to DIV_GATE
If without this patches, audio mclk might not work
[Release-log]
N/A
Change-Id: Ica79e93db8418dfb3f223b487e26a0885ebdef84
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6625348
Build: srv_hbgsm110
diff --git a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
index 86111c4..b0cefe9 100644
--- a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
+++ b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
@@ -618,8 +618,9 @@
0x0020, 0x0024, 6, 2, -1, -1, -1),
};
-static const struct mtk_clk_divider top_adj_divs[] = {
- DIV_ADJ(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", 0x0420, 8, 8),
+static struct mtk_composite top_aud_divs[] = {
+ DIV_GATE(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
+ 0x0420, 0, 0x0420, 8, 8),
};
static const struct mtk_gate_regs infra0_cg_regs = {
@@ -1033,9 +1034,8 @@
mt7988_top_clk_data);
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
&mt7988_clk_lock, mt7988_top_clk_data);
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
- &mt7988_clk_lock, mt7988_top_clk_data);
-
+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
+ base, &mt7988_clk_lock, mt7988_top_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get,
mt7988_top_clk_data);