blob: 925a852451642692602fdbb6a04de459a4a3f307 [file] [log] [blame]
developer1b76b3f2021-12-22 19:53:19 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
developer3c21f192022-03-14 20:37:51 +08006 model = "MediaTek MT7986a gsw RFB";
developer1b76b3f2021-12-22 19:53:19 +08007 compatible = "mediatek,mt7986a-2500wan-gsw-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 gsw: gsw@0 {
14 compatible = "mediatek,mt753x";
15 mediatek,ethsys = <&ethsys>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19
20 memory {
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 sound {
25 compatible = "mediatek,mt7986-wm8960-machine";
26 mediatek,platform = <&afe>;
27 audio-routing = "Headphone", "HP_L",
28 "Headphone", "HP_R",
29 "LINPUT1", "AMIC",
30 "RINPUT1", "AMIC";
31 mediatek,audio-codec = <&wm8960>;
32 status = "okay";
33 };
34};
35
developer209e52d2022-06-30 11:32:57 +080036&fan {
37 pwms = <&pwm 1 50000 0>;
38 status = "disabled";
39};
40
developer1b76b3f2021-12-22 19:53:19 +080041&pwm {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
44 status = "okay";
45};
46
47&uart0 {
48 status = "okay";
49};
50
51&uart1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&uart1_pins>;
54 status = "okay";
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
developera2613e62022-07-01 18:29:37 +080060 status = "disabled";
developer1b76b3f2021-12-22 19:53:19 +080061};
62
63&i2c0 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&i2c_pins>;
66 status = "okay";
67
68 wm8960: wm8960@1a {
69 compatible = "wlf,wm8960";
70 reg = <0x1a>;
71 };
72};
73
74&auxadc {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080089
90 fixed-link {
91 speed = <2500>;
92 full-duplex;
93 pause;
94 link-gpio = <&pio 47 0>;
95 phy-handle = <&phy5>;
96 label = "lan5";
97 };
developer1b76b3f2021-12-22 19:53:19 +080098 };
99
100 gmac1: mac@1 {
101 compatible = "mediatek,eth-mac";
102 reg = <1>;
103 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +0800104 phy-handle = <&phy6>;
developer1b76b3f2021-12-22 19:53:19 +0800105 };
106
107 mdio: mdio-bus {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
developerf0a1e452022-08-15 12:06:11 +0800111 reset-gpios = <&pio 6 1>;
112 reset-delay-us = <600>;
113
developer1b76b3f2021-12-22 19:53:19 +0800114 phy5: phy@5 {
developer283fc452022-08-18 19:50:33 +0800115 compatible = "ethernet-phy-id67c9.de0a";
developer1b76b3f2021-12-22 19:53:19 +0800116 reg = <5>;
developer1b76b3f2021-12-22 19:53:19 +0800117 };
118
119 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +0800120 compatible = "ethernet-phy-ieee802.3-c45";
developer1b76b3f2021-12-22 19:53:19 +0800121 reg = <6>;
developer1b76b3f2021-12-22 19:53:19 +0800122 };
developer1b76b3f2021-12-22 19:53:19 +0800123 };
124};
125
126&gsw {
127 mediatek,mdio = <&mdio>;
128 mediatek,portmap = "lllll";
129 mediatek,mdio_master_pinmux = <1>;
130 reset-gpios = <&pio 5 0>;
131 interrupt-parent = <&pio>;
132 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
133 status = "okay";
134
135 port5: port@5 {
136 compatible = "mediatek,mt753x-port";
137 reg = <5>;
138 phy-mode = "sgmii";
139
140 fixed-link {
141 speed = <2500>;
142 full-duplex;
143 };
144
145 };
146
147 port6: port@6 {
148 compatible = "mediatek,mt753x-port";
developer3c21f192022-03-14 20:37:51 +0800149 /* mediatek,ssc-on; */
developer1b76b3f2021-12-22 19:53:19 +0800150 reg = <6>;
151 phy-mode = "sgmii";
152 fixed-link {
153 speed = <2500>;
154 full-duplex;
155 };
156 };
157};
158
159&hnat {
160 mtketh-wan = "eth1";
developer3c21f192022-03-14 20:37:51 +0800161 mtketh-lan = "eth0";
developer1b76b3f2021-12-22 19:53:19 +0800162 mtketh-max-gmac = <2>;
163 status = "okay";
164};
165
166&spi0 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&spi_flash_pins>;
169 cs-gpios = <0>, <0>;
170 status = "okay";
171
172 spi_nor@0 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 compatible = "jedec,spi-nor";
176 reg = <0>;
177 spi-max-frequency = <20000000>;
178 spi-tx-buswidth = <4>;
179 spi-rx-buswidth = <4>;
180 };
181
182 spi_nand: spi_nand@1 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "spi-nand";
186 reg = <1>;
187 spi-max-frequency = <20000000>;
188 spi-tx-buswidth = <4>;
189 spi-rx-buswidth = <4>;
190 };
191};
192
193&spi1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&spic_pins_g2>;
196 status = "okay";
197};
198
199&pcie0 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pcie0_pins>;
202 status = "okay";
203};
204
205&wbsys {
206 mediatek,mtd-eeprom = <&factory 0x0000>;
207 status = "okay";
208};
209
210&pio {
211 spi_flash_pins: spi-flash-pins-33-to-38 {
212 mux {
213 function = "flash";
214 groups = "spi0", "spi0_wp_hold";
215 };
216 conf-pu {
217 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
218 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800219 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800220 };
221 conf-pd {
222 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
223 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800224 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800225 };
226 };
227};