blob: 4515b587b741f52fdb22af779ae57348c18e4871 [file] [log] [blame]
developer1b76b3f2021-12-22 19:53:19 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
developer3c21f192022-03-14 20:37:51 +08006 model = "MediaTek MT7986a gsw RFB";
developer1b76b3f2021-12-22 19:53:19 +08007 compatible = "mediatek,mt7986a-2500wan-gsw-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 gsw: gsw@0 {
14 compatible = "mediatek,mt753x";
15 mediatek,ethsys = <&ethsys>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19
20 memory {
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 sound {
25 compatible = "mediatek,mt7986-wm8960-machine";
26 mediatek,platform = <&afe>;
27 audio-routing = "Headphone", "HP_L",
28 "Headphone", "HP_R",
29 "LINPUT1", "AMIC",
30 "RINPUT1", "AMIC";
31 mediatek,audio-codec = <&wm8960>;
32 status = "okay";
33 };
34};
35
developer209e52d2022-06-30 11:32:57 +080036&fan {
37 pwms = <&pwm 1 50000 0>;
38 status = "disabled";
39};
40
developer1b76b3f2021-12-22 19:53:19 +080041&pwm {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
44 status = "okay";
45};
46
47&uart0 {
48 status = "okay";
49};
50
51&uart1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&uart1_pins>;
54 status = "okay";
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
developera2613e62022-07-01 18:29:37 +080060 status = "disabled";
developer1b76b3f2021-12-22 19:53:19 +080061};
62
63&i2c0 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&i2c_pins>;
66 status = "okay";
67
68 wm8960: wm8960@1a {
69 compatible = "wlf,wm8960";
70 reg = <0x1a>;
71 };
72};
73
74&auxadc {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080089 phy-handle = <&phy5>;
developer1b76b3f2021-12-22 19:53:19 +080090 };
91
92 gmac1: mac@1 {
93 compatible = "mediatek,eth-mac";
94 reg = <1>;
95 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080096 phy-handle = <&phy6>;
developer1b76b3f2021-12-22 19:53:19 +080097 };
98
99 mdio: mdio-bus {
100 #address-cells = <1>;
101 #size-cells = <0>;
102
developerf0a1e452022-08-15 12:06:11 +0800103 reset-gpios = <&pio 6 1>;
104 reset-delay-us = <600>;
105
developer1b76b3f2021-12-22 19:53:19 +0800106 phy5: phy@5 {
developerf0a1e452022-08-15 12:06:11 +0800107 compatible = "ethernet-phy-ieee802.3-c45";
developer1b76b3f2021-12-22 19:53:19 +0800108 reg = <5>;
developer1b76b3f2021-12-22 19:53:19 +0800109 };
110
111 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +0800112 compatible = "ethernet-phy-ieee802.3-c45";
developer1b76b3f2021-12-22 19:53:19 +0800113 reg = <6>;
developer1b76b3f2021-12-22 19:53:19 +0800114 };
developer1b76b3f2021-12-22 19:53:19 +0800115 };
116};
117
118&gsw {
119 mediatek,mdio = <&mdio>;
120 mediatek,portmap = "lllll";
121 mediatek,mdio_master_pinmux = <1>;
122 reset-gpios = <&pio 5 0>;
123 interrupt-parent = <&pio>;
124 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
125 status = "okay";
126
127 port5: port@5 {
128 compatible = "mediatek,mt753x-port";
129 reg = <5>;
130 phy-mode = "sgmii";
131
132 fixed-link {
133 speed = <2500>;
134 full-duplex;
135 };
136
137 };
138
139 port6: port@6 {
140 compatible = "mediatek,mt753x-port";
developer3c21f192022-03-14 20:37:51 +0800141 /* mediatek,ssc-on; */
developer1b76b3f2021-12-22 19:53:19 +0800142 reg = <6>;
143 phy-mode = "sgmii";
144 fixed-link {
145 speed = <2500>;
146 full-duplex;
147 };
148 };
149};
150
151&hnat {
152 mtketh-wan = "eth1";
developer3c21f192022-03-14 20:37:51 +0800153 mtketh-lan = "eth0";
developer1b76b3f2021-12-22 19:53:19 +0800154 mtketh-max-gmac = <2>;
155 status = "okay";
156};
157
158&spi0 {
159 pinctrl-names = "default";
160 pinctrl-0 = <&spi_flash_pins>;
161 cs-gpios = <0>, <0>;
162 status = "okay";
163
164 spi_nor@0 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "jedec,spi-nor";
168 reg = <0>;
169 spi-max-frequency = <20000000>;
170 spi-tx-buswidth = <4>;
171 spi-rx-buswidth = <4>;
172 };
173
174 spi_nand: spi_nand@1 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 compatible = "spi-nand";
178 reg = <1>;
179 spi-max-frequency = <20000000>;
180 spi-tx-buswidth = <4>;
181 spi-rx-buswidth = <4>;
182 };
183};
184
185&spi1 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&spic_pins_g2>;
188 status = "okay";
189};
190
191&pcie0 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pcie0_pins>;
194 status = "okay";
195};
196
197&wbsys {
198 mediatek,mtd-eeprom = <&factory 0x0000>;
199 status = "okay";
200};
201
202&pio {
203 spi_flash_pins: spi-flash-pins-33-to-38 {
204 mux {
205 function = "flash";
206 groups = "spi0", "spi0_wp_hold";
207 };
208 conf-pu {
209 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
210 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800211 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800212 };
213 conf-pd {
214 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
215 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800216 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800217 };
218 };
219};