blob: 457c35169c0d87aa34d22e41b225f7f3bb55f82b [file] [log] [blame]
developer1b76b3f2021-12-22 19:53:19 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
developer3c21f192022-03-14 20:37:51 +08006 model = "MediaTek MT7986a gsw RFB";
developer1b76b3f2021-12-22 19:53:19 +08007 compatible = "mediatek,mt7986a-2500wan-gsw-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 gsw: gsw@0 {
14 compatible = "mediatek,mt753x";
15 mediatek,ethsys = <&ethsys>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19
20 memory {
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 sound {
25 compatible = "mediatek,mt7986-wm8960-machine";
26 mediatek,platform = <&afe>;
27 audio-routing = "Headphone", "HP_L",
28 "Headphone", "HP_R",
29 "LINPUT1", "AMIC",
30 "RINPUT1", "AMIC";
31 mediatek,audio-codec = <&wm8960>;
32 status = "okay";
33 };
34};
35
developer209e52d2022-06-30 11:32:57 +080036&fan {
37 pwms = <&pwm 1 50000 0>;
38 status = "disabled";
39};
40
developer1b76b3f2021-12-22 19:53:19 +080041&pwm {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
44 status = "okay";
45};
46
47&uart0 {
48 status = "okay";
49};
50
51&uart1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&uart1_pins>;
54 status = "okay";
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
60 status = "okay";
61};
62
63&i2c0 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&i2c_pins>;
66 status = "okay";
67
68 wm8960: wm8960@1a {
69 compatible = "wlf,wm8960";
70 reg = <0x1a>;
71 };
72};
73
74&auxadc {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
89
90 fixed-link {
91 speed = <2500>;
92 full-duplex;
93 pause;
94 };
95 };
96
97 gmac1: mac@1 {
98 compatible = "mediatek,eth-mac";
99 reg = <1>;
100 phy-mode = "2500base-x";
101
102 fixed-link {
103 speed = <2500>;
104 full-duplex;
105 pause;
106 };
107 };
108
109 mdio: mdio-bus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 phy5: phy@5 {
114 compatible = "ethernet-phy-id67c9.de0a";
115 reg = <5>;
116 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800117 reset-assert-us = <600>;
developer1b76b3f2021-12-22 19:53:19 +0800118 reset-deassert-us = <20000>;
119 phy-mode = "2500base-x";
120 };
121
122 phy6: phy@6 {
123 compatible = "ethernet-phy-id67c9.de0a";
124 reg = <6>;
125 phy-mode = "2500base-x";
126 };
127
128 };
129};
130
131&gsw {
132 mediatek,mdio = <&mdio>;
133 mediatek,portmap = "lllll";
134 mediatek,mdio_master_pinmux = <1>;
135 reset-gpios = <&pio 5 0>;
136 interrupt-parent = <&pio>;
137 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
138 status = "okay";
139
140 port5: port@5 {
141 compatible = "mediatek,mt753x-port";
142 reg = <5>;
143 phy-mode = "sgmii";
144
145 fixed-link {
146 speed = <2500>;
147 full-duplex;
148 };
149
150 };
151
152 port6: port@6 {
153 compatible = "mediatek,mt753x-port";
developer3c21f192022-03-14 20:37:51 +0800154 /* mediatek,ssc-on; */
developer1b76b3f2021-12-22 19:53:19 +0800155 reg = <6>;
156 phy-mode = "sgmii";
157 fixed-link {
158 speed = <2500>;
159 full-duplex;
160 };
161 };
162};
163
164&hnat {
165 mtketh-wan = "eth1";
developer3c21f192022-03-14 20:37:51 +0800166 mtketh-lan = "eth0";
developer1b76b3f2021-12-22 19:53:19 +0800167 mtketh-max-gmac = <2>;
168 status = "okay";
169};
170
171&spi0 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&spi_flash_pins>;
174 cs-gpios = <0>, <0>;
175 status = "okay";
176
177 spi_nor@0 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 compatible = "jedec,spi-nor";
181 reg = <0>;
182 spi-max-frequency = <20000000>;
183 spi-tx-buswidth = <4>;
184 spi-rx-buswidth = <4>;
185 };
186
187 spi_nand: spi_nand@1 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "spi-nand";
191 reg = <1>;
192 spi-max-frequency = <20000000>;
193 spi-tx-buswidth = <4>;
194 spi-rx-buswidth = <4>;
195 };
196};
197
198&spi1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&spic_pins_g2>;
201 status = "okay";
202};
203
204&pcie0 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pcie0_pins>;
207 status = "okay";
208};
209
210&wbsys {
211 mediatek,mtd-eeprom = <&factory 0x0000>;
212 status = "okay";
213};
214
215&pio {
216 spi_flash_pins: spi-flash-pins-33-to-38 {
217 mux {
218 function = "flash";
219 groups = "spi0", "spi0_wp_hold";
220 };
221 conf-pu {
222 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
223 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800224 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800225 };
226 conf-pd {
227 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
228 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800229 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer1b76b3f2021-12-22 19:53:19 +0800230 };
231 };
232};