blob: 0e55e52b765cf7558235d6ab6378616313474d17 [file] [log] [blame]
developerab4a0b82023-08-18 19:56:34 +08001From 11e837febd8092b39d13b74c76d9134496c6e9d4 Mon Sep 17 00:00:00 2001
developerf64861f2022-06-22 11:44:53 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developerab4a0b82023-08-18 19:56:34 +08004Subject: [PATCH] wifi: mt76: mt7915: add mtk internal debug tools for mt76
developere2cc0fa2022-03-29 17:31:03 +08005
6---
developerc04f5402023-02-03 09:22:26 +08007 mt76_connac_mcu.h | 6 +
developer5ce5ea42022-08-31 14:12:29 +08008 mt7915/Makefile | 2 +-
developer7f190632023-03-21 18:13:05 +08009 mt7915/debugfs.c | 89 +-
developer5ce5ea42022-08-31 14:12:29 +080010 mt7915/mac.c | 14 +
developerab4a0b82023-08-18 19:56:34 +080011 mt7915/main.c | 5 +
developerc04f5402023-02-03 09:22:26 +080012 mt7915/mcu.c | 48 +-
developer5ce5ea42022-08-31 14:12:29 +080013 mt7915/mcu.h | 4 +
developereb2bd8e2023-02-09 11:16:04 +080014 mt7915/mt7915.h | 43 +
developer2324aa22023-04-12 11:30:15 +080015 mt7915/mt7915_debug.h | 1418 ++++++++++++++++
developerab4a0b82023-08-18 19:56:34 +080016 mt7915/mtk_debugfs.c | 3622 +++++++++++++++++++++++++++++++++++++++++
developer5ce5ea42022-08-31 14:12:29 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developerab4a0b82023-08-18 19:56:34 +080019 12 files changed, 5327 insertions(+), 19 deletions(-)
developer5ce5ea42022-08-31 14:12:29 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developere2cc0fa2022-03-29 17:31:03 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer849549c2023-08-02 17:26:48 +080025index bd0bf4bb..ab3b58e1 100644
developere2cc0fa2022-03-29 17:31:03 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developer2157bf82023-06-26 02:27:49 +080028@@ -1151,6 +1151,7 @@ enum {
developer711759c2022-09-21 18:38:10 +080029 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developer2157bf82023-06-26 02:27:49 +080036@@ -1174,6 +1175,11 @@ enum {
developere2cc0fa2022-03-29 17:31:03 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
developere2cc0fa2022-03-29 17:31:03 +080041+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
42+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
43+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
44+#endif
45 MCU_EXT_CMD_TXDPD_CAL = 0x60,
46 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerc04f5402023-02-03 09:22:26 +080047 MCU_EXT_CMD_RED_ENABLE = 0x68,
developere2cc0fa2022-03-29 17:31:03 +080048diff --git a/mt7915/Makefile b/mt7915/Makefile
developer849549c2023-08-02 17:26:48 +080049index c4dca9c1..fd711416 100644
developere2cc0fa2022-03-29 17:31:03 +080050--- a/mt7915/Makefile
51+++ b/mt7915/Makefile
developerc04f5402023-02-03 09:22:26 +080052@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developere2cc0fa2022-03-29 17:31:03 +080053 obj-$(CONFIG_MT7915E) += mt7915e.o
54
55 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
56- debugfs.o mmio.o
57+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
58
59 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerbbd45e12023-05-19 08:22:06 +080060 mt7915e-$(CONFIG_MT798X_WMAC) += soc.o
developere2cc0fa2022-03-29 17:31:03 +080061diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developer849549c2023-08-02 17:26:48 +080062index 93e549c3..f1813776 100644
developere2cc0fa2022-03-29 17:31:03 +080063--- a/mt7915/debugfs.c
64+++ b/mt7915/debugfs.c
65@@ -8,6 +8,9 @@
66 #include "mac.h"
67
68 #define FW_BIN_LOG_MAGIC 0x44e98caf
69+#ifdef MTK_DEBUG
70+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
71+#endif
72
73 /** global debugfs **/
74
developer2157bf82023-06-26 02:27:49 +080075@@ -496,6 +499,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developere2cc0fa2022-03-29 17:31:03 +080076 int ret;
77
developerbd398d52022-06-06 20:53:24 +080078 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developere2cc0fa2022-03-29 17:31:03 +080079+#ifdef MTK_DEBUG
developerbd398d52022-06-06 20:53:24 +080080+ dev->fw.debug_wm = val;
developere2cc0fa2022-03-29 17:31:03 +080081+#endif
82
developerbd398d52022-06-06 20:53:24 +080083 if (dev->fw.debug_bin)
developere2cc0fa2022-03-29 17:31:03 +080084 val = 16;
developer2157bf82023-06-26 02:27:49 +080085@@ -520,6 +526,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developere2cc0fa2022-03-29 17:31:03 +080086 if (ret)
developerbd398d52022-06-06 20:53:24 +080087 goto out;
developere2cc0fa2022-03-29 17:31:03 +080088 }
89+#ifdef MTK_DEBUG
90+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
91+#endif
92
93 /* WM CPU info record control */
94 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer2157bf82023-06-26 02:27:49 +080095@@ -527,6 +536,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developere2cc0fa2022-03-29 17:31:03 +080096 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
97 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
98
99+#ifdef MTK_DEBUG
developerbd398d52022-06-06 20:53:24 +0800100+ if (dev->fw.debug_bin & BIT(3))
developere2cc0fa2022-03-29 17:31:03 +0800101+ /* use bit 7 to indicate v2 magic number */
developerbd398d52022-06-06 20:53:24 +0800102+ dev->fw.debug_wm |= BIT(7);
developere2cc0fa2022-03-29 17:31:03 +0800103+#endif
104+
developerbd398d52022-06-06 20:53:24 +0800105 out:
106 if (ret)
107 dev->fw.debug_wm = 0;
developer2157bf82023-06-26 02:27:49 +0800108@@ -539,7 +554,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developere2cc0fa2022-03-29 17:31:03 +0800109 {
110 struct mt7915_dev *dev = data;
111
developerbd398d52022-06-06 20:53:24 +0800112- *val = dev->fw.debug_wm;
developere2cc0fa2022-03-29 17:31:03 +0800113+#ifdef MTK_DEBUG
developerbd398d52022-06-06 20:53:24 +0800114+ *val = dev->fw.debug_wm & ~BIT(7);
developere2cc0fa2022-03-29 17:31:03 +0800115+#else
developerbd398d52022-06-06 20:53:24 +0800116+ val = dev->fw.debug_wm;
developere2cc0fa2022-03-29 17:31:03 +0800117+#endif
118
119 return 0;
120 }
developer2157bf82023-06-26 02:27:49 +0800121@@ -614,16 +633,30 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developer7f190632023-03-21 18:13:05 +0800122 };
123 struct mt7915_dev *dev = data;
124
125- if (!dev->relay_fwlog)
126+ if (!dev->relay_fwlog && val) {
127 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
128 1500, 512, &relay_cb, NULL);
129- if (!dev->relay_fwlog)
130- return -ENOMEM;
131+ if (!dev->relay_fwlog)
132+ return -ENOMEM;
133+ }
134
135 dev->fw.debug_bin = val;
developere2cc0fa2022-03-29 17:31:03 +0800136
137 relay_reset(dev->relay_fwlog);
138
139+#ifdef MTK_DEBUG
140+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
141+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
142+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
143+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
144+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
developere2cc0fa2022-03-29 17:31:03 +0800145+#endif
146+
developer7f190632023-03-21 18:13:05 +0800147+ if (dev->relay_fwlog && !val) {
148+ relay_close(dev->relay_fwlog);
149+ dev->relay_fwlog = NULL;
150+ }
developerbd398d52022-06-06 20:53:24 +0800151+
152 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developere2cc0fa2022-03-29 17:31:03 +0800153 }
154
developer12a42792023-07-29 05:30:55 +0800155@@ -1253,6 +1286,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developere2cc0fa2022-03-29 17:31:03 +0800156 if (!ext_phy)
157 dev->debugfs_dir = dir;
158
159+#ifdef MTK_DEBUG
160+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
161+ mt7915_mtk_init_debugfs(phy, dir);
162+#endif
163+
164 return 0;
165 }
166
developer12a42792023-07-29 05:30:55 +0800167@@ -1265,6 +1303,12 @@ mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen,
developer7f190632023-03-21 18:13:05 +0800168 void *dest;
169
170 spin_lock_irqsave(&lock, flags);
171+
172+ if (!dev->relay_fwlog) {
173+ spin_unlock_irqrestore(&lock, flags);
174+ return;
175+ }
176+
177 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
178 if (dest) {
179 *(u32 *)dest = hdrlen + len;
developer12a42792023-07-29 05:30:55 +0800180@@ -1293,17 +1337,50 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developere2cc0fa2022-03-29 17:31:03 +0800181 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
182 };
183
developer7f190632023-03-21 18:13:05 +0800184- if (!dev->relay_fwlog)
185- return;
developere2cc0fa2022-03-29 17:31:03 +0800186+#ifdef MTK_DEBUG
187+ struct {
188+ __le32 magic;
189+ u8 version;
190+ u8 _rsv;
191+ __le16 serial_id;
192+ __le32 timestamp;
193+ __le16 msg_type;
194+ __le16 len;
195+ } hdr2 = {
196+ .version = 0x1,
197+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
198+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
199+ };
200+#endif
developere2cc0fa2022-03-29 17:31:03 +0800201
202+#ifdef MTK_DEBUG
203+ /* old magic num */
developerbd398d52022-06-06 20:53:24 +0800204+ if (!(dev->fw.debug_wm & BIT(7))) {
developere2cc0fa2022-03-29 17:31:03 +0800205+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
206+ hdr.len = *(__le16 *)data;
207+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
208+ } else {
209+ hdr2.serial_id = dev->dbg.fwlog_seq++;
210+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
211+ hdr2.len = *(__le16 *)data;
212+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
213+ }
214+#else
215 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
216 hdr.len = *(__le16 *)data;
217 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
218+#endif
219 }
220
221 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
222 {
223+#ifdef MTK_DEBUG
224+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
225+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
226+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
227+#else
228 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
229+#endif
230 return false;
231
232 if (dev->relay_fwlog)
233diff --git a/mt7915/mac.c b/mt7915/mac.c
developer849549c2023-08-02 17:26:48 +0800234index d9d5aad4..d22a4079 100644
developere2cc0fa2022-03-29 17:31:03 +0800235--- a/mt7915/mac.c
236+++ b/mt7915/mac.c
developerbbd45e12023-05-19 08:22:06 +0800237@@ -275,6 +275,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developere2cc0fa2022-03-29 17:31:03 +0800238 __le16 fc = 0;
239 int idx;
240
241+#ifdef MTK_DEBUG
242+ if (dev->dbg.dump_rx_raw)
243+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
244+#endif
245 memset(status, 0, sizeof(*status));
246
developereb6a0182022-12-12 18:53:32 +0800247 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developer2157bf82023-06-26 02:27:49 +0800248@@ -459,6 +463,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developere2cc0fa2022-03-29 17:31:03 +0800249 }
250
251 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
252+#ifdef MTK_DEBUG
253+ if (dev->dbg.dump_rx_pkt)
254+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
255+#endif
256 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developerf64861f2022-06-22 11:44:53 +0800257 struct ieee80211_vif *vif;
258 int err;
developer2157bf82023-06-26 02:27:49 +0800259@@ -796,6 +804,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developere2cc0fa2022-03-29 17:31:03 +0800260 tx_info->buf[1].skip_unmap = true;
261 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
262
263+#ifdef MTK_DEBUG
264+ if (dev->dbg.dump_txd)
265+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
266+ if (dev->dbg.dump_tx_pkt)
267+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
268+#endif
269 return 0;
270 }
271
developerc115a812022-06-22 15:29:14 +0800272diff --git a/mt7915/main.c b/mt7915/main.c
developerab4a0b82023-08-18 19:56:34 +0800273index 4e5c138f..b6dc9513 100644
developerc115a812022-06-22 15:29:14 +0800274--- a/mt7915/main.c
275+++ b/mt7915/main.c
developer9851a292022-12-15 17:33:43 +0800276@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developerc115a812022-06-22 15:29:14 +0800277 if (ret)
278 goto out;
279
280+#ifdef MTK_DEBUG
281+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
282+#else
283 ret = mt7915_mcu_set_sku_en(phy, true);
284+#endif
285 if (ret)
286 goto out;
287
developerab4a0b82023-08-18 19:56:34 +0800288@@ -253,6 +257,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
289 mvif->sta.wcid.phy_idx = ext_phy;
290 mvif->sta.wcid.hw_key_idx = -1;
291 mvif->sta.wcid.tx_info |= MT_WCID_TX_INFO_SET;
292+ mvif->sta.vif = mvif;
293 mt76_packet_id_init(&mvif->sta.wcid);
294
295 mt7915_mac_wtbl_update(dev, idx,
developere2cc0fa2022-03-29 17:31:03 +0800296diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerab4a0b82023-08-18 19:56:34 +0800297index 03f84343..6b19af74 100644
developere2cc0fa2022-03-29 17:31:03 +0800298--- a/mt7915/mcu.c
299+++ b/mt7915/mcu.c
developer2157bf82023-06-26 02:27:49 +0800300@@ -205,6 +205,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developerf64861f2022-06-22 11:44:53 +0800301 else
302 qid = MT_MCUQ_WM;
developere2cc0fa2022-03-29 17:31:03 +0800303
developere2cc0fa2022-03-29 17:31:03 +0800304+#ifdef MTK_DEBUG
305+ if (dev->dbg.dump_mcu_pkt)
306+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
307+#endif
developerf64861f2022-06-22 11:44:53 +0800308+
309 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
310 }
developere2cc0fa2022-03-29 17:31:03 +0800311
developerc1571f92023-07-04 22:11:24 +0800312@@ -2288,7 +2293,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
developerc04f5402023-02-03 09:22:26 +0800313 sizeof(req), false);
314 }
315
316-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
317+#ifndef MTK_DEBUG
318+static
319+#endif
320+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
321 {
322 #define RED_DISABLE 0
323 #define RED_BY_WA_ENABLE 2
developerab4a0b82023-08-18 19:56:34 +0800324@@ -3352,6 +3360,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developerc115a812022-06-22 15:29:14 +0800325 .sku_enable = enable,
326 };
327
328+ pr_info("%s: enable = %d\n", __func__, enable);
329+
330 return mt76_mcu_send_msg(&dev->mt76,
331 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
332 sizeof(req), true);
developerab4a0b82023-08-18 19:56:34 +0800333@@ -4006,6 +4016,23 @@ out:
developer2157bf82023-06-26 02:27:49 +0800334 return ret;
developere2cc0fa2022-03-29 17:31:03 +0800335 }
developerb10f1382022-04-21 20:09:33 +0800336
developere2cc0fa2022-03-29 17:31:03 +0800337+#ifdef MTK_DEBUG
338+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
339+{
340+ struct {
341+ __le32 args[3];
342+ } req = {
343+ .args = {
344+ cpu_to_le32(a1),
345+ cpu_to_le32(a2),
346+ cpu_to_le32(a3),
347+ },
348+ };
349+
350+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
351+}
developere2cc0fa2022-03-29 17:31:03 +0800352+#endif
developerb10f1382022-04-21 20:09:33 +0800353+
354 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
355 {
356 struct {
developerab4a0b82023-08-18 19:56:34 +0800357@@ -4034,3 +4061,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer711759c2022-09-21 18:38:10 +0800358
359 return 0;
360 }
361+
362+#ifdef MTK_DEBUG
363+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
364+{
365+ struct {
366+ u16 action;
367+ u8 _rsv1[2];
368+ u16 wcid;
369+ u8 enable;
370+ u8 _rsv2[5];
371+ } __packed req = {
372+ .action = cpu_to_le16(1),
373+ .wcid = cpu_to_le16(wcid),
374+ .enable = enable,
375+ };
376+
377+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
378+}
379+#endif
developere2cc0fa2022-03-29 17:31:03 +0800380diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer849549c2023-08-02 17:26:48 +0800381index 8f365461..dd3b5062 100644
developere2cc0fa2022-03-29 17:31:03 +0800382--- a/mt7915/mcu.h
383+++ b/mt7915/mcu.h
developerbbd45e12023-05-19 08:22:06 +0800384@@ -333,6 +333,10 @@ enum {
developere2cc0fa2022-03-29 17:31:03 +0800385 MCU_WA_PARAM_PDMA_RX = 0x04,
386 MCU_WA_PARAM_CPU_UTIL = 0x0b,
387 MCU_WA_PARAM_RED = 0x0e,
388+#ifdef MTK_DEBUG
389+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
390+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
391+#endif
developerc04f5402023-02-03 09:22:26 +0800392 MCU_WA_PARAM_RED_SETTING = 0x40,
developere2cc0fa2022-03-29 17:31:03 +0800393 };
394
developere2cc0fa2022-03-29 17:31:03 +0800395diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerab4a0b82023-08-18 19:56:34 +0800396index 24d8da28..f9e6917c 100644
developere2cc0fa2022-03-29 17:31:03 +0800397--- a/mt7915/mt7915.h
398+++ b/mt7915/mt7915.h
399@@ -9,6 +9,7 @@
400 #include "../mt76_connac.h"
401 #include "regs.h"
402
403+#define MTK_DEBUG 1
404 #define MT7915_MAX_INTERFACES 19
developere2cc0fa2022-03-29 17:31:03 +0800405 #define MT7915_WTBL_SIZE 288
developerf64861f2022-06-22 11:44:53 +0800406 #define MT7916_WTBL_SIZE 544
developerab4a0b82023-08-18 19:56:34 +0800407@@ -320,6 +321,28 @@ struct mt7915_dev {
developere2cc0fa2022-03-29 17:31:03 +0800408 struct reset_control *rstc;
409 void __iomem *dcm;
410 void __iomem *sku;
411+
412+#ifdef MTK_DEBUG
413+ u16 wlan_idx;
414+ struct {
415+ u32 fixed_rate;
416+ u32 l1debugfs_reg;
417+ u32 l2debugfs_reg;
418+ u32 mac_reg;
419+ u32 fw_dbg_module;
420+ u8 fw_dbg_lv;
421+ u32 bcn_total_cnt[2];
422+ u16 fwlog_seq;
423+ bool dump_mcu_pkt;
424+ bool dump_txd;
425+ bool dump_tx_pkt;
426+ bool dump_rx_pkt;
427+ bool dump_rx_raw;
428+ u32 token_idx;
developerc115a812022-06-22 15:29:14 +0800429+ u8 sku_disable;
developere2cc0fa2022-03-29 17:31:03 +0800430+ } dbg;
431+ const struct mt7915_dbg_reg_desc *dbg_reg;
432+#endif
433 };
434
435 enum {
developerab4a0b82023-08-18 19:56:34 +0800436@@ -599,4 +622,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerc226de82022-10-03 12:24:57 +0800437 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
438 bool pci, int *irq);
developere2cc0fa2022-03-29 17:31:03 +0800439
440+#ifdef MTK_DEBUG
441+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
442+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
443+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
444+void mt7915_dump_tmac_info(u8 *tmac_info);
445+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
446+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer711759c2022-09-21 18:38:10 +0800447+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developere2cc0fa2022-03-29 17:31:03 +0800448+
449+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
450+enum {
451+ PKT_BIN_DEBUG_MCU,
452+ PKT_BIN_DEBUG_TXD,
453+ PKT_BIN_DEBUG_TX,
454+ PKT_BIN_DEBUG_RX,
455+ PKT_BIN_DEBUG_RX_RAW,
456+};
457+
458+#endif
459+
460 #endif
461diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
462new file mode 100644
developer849549c2023-08-02 17:26:48 +0800463index 00000000..fa8794fd
developere2cc0fa2022-03-29 17:31:03 +0800464--- /dev/null
465+++ b/mt7915/mt7915_debug.h
developer2324aa22023-04-12 11:30:15 +0800466@@ -0,0 +1,1418 @@
developere2cc0fa2022-03-29 17:31:03 +0800467+#ifndef __MT7915_DEBUG_H
468+#define __MT7915_DEBUG_H
469+
470+#ifdef MTK_DEBUG
471+
472+#define DBG_INVALID_BASE 0xffffffff
473+#define DBG_INVALID_OFFSET 0x0
474+
475+struct __dbg_map {
476+ u32 phys;
477+ u32 maps;
478+ u32 size;
479+};
480+
481+struct __dbg_reg {
482+ u32 base;
483+ u32 offs;
484+};
485+
486+struct __dbg_mask {
487+ u32 end;
488+ u32 start;
489+};
490+
491+enum dbg_base_rev {
492+ MT_DBG_WFDMA0_BASE,
493+ MT_DBG_WFDMA1_BASE,
494+ MT_DBG_WFDMA0_PCIE1_BASE,
495+ MT_DBG_WFDMA1_PCIE1_BASE,
496+ MT_DBG_WFDMA_EXT_CSR_BASE,
497+ MT_DBG_SWDEF_BASE,
498+ __MT_DBG_BASE_REV_MAX,
499+};
500+
501+enum dbg_reg_rev {
502+ DBG_INT_SOURCE_CSR,
503+ DBG_INT_MASK_CSR,
504+ DBG_INT1_SOURCE_CSR,
505+ DBG_INT1_MASK_CSR,
506+ DBG_TX_RING_BASE,
507+ DBG_RX_EVENT_RING_BASE,
508+ DBG_RX_STS_RING_BASE,
509+ DBG_RX_DATA_RING_BASE,
510+ DBG_DMA_ICSC_FR0,
511+ DBG_DMA_ICSC_FR1,
512+ DBG_TMAC_ICSCR0,
513+ DBG_RMAC_RXICSRPT,
514+ DBG_MIB_M0SDR0,
515+ DBG_MIB_M0SDR3,
516+ DBG_MIB_M0SDR4,
517+ DBG_MIB_M0SDR5,
518+ DBG_MIB_M0SDR7,
519+ DBG_MIB_M0SDR8,
520+ DBG_MIB_M0SDR9,
521+ DBG_MIB_M0SDR10,
522+ DBG_MIB_M0SDR11,
523+ DBG_MIB_M0SDR12,
524+ DBG_MIB_M0SDR14,
525+ DBG_MIB_M0SDR15,
526+ DBG_MIB_M0SDR16,
527+ DBG_MIB_M0SDR17,
528+ DBG_MIB_M0SDR18,
529+ DBG_MIB_M0SDR19,
530+ DBG_MIB_M0SDR20,
531+ DBG_MIB_M0SDR21,
532+ DBG_MIB_M0SDR22,
533+ DBG_MIB_M0SDR23,
534+ DBG_MIB_M0DR0,
535+ DBG_MIB_M0DR1,
536+ DBG_MIB_MUBF,
537+ DBG_MIB_M0DR6,
538+ DBG_MIB_M0DR7,
539+ DBG_MIB_M0DR8,
540+ DBG_MIB_M0DR9,
541+ DBG_MIB_M0DR10,
542+ DBG_MIB_M0DR11,
543+ DBG_MIB_M0DR12,
544+ DBG_WTBLON_WDUCR,
545+ DBG_UWTBL_WDUCR,
546+ DBG_PLE_DRR_TABLE_CTRL,
547+ DBG_PLE_DRR_TABLE_RDATA,
548+ DBG_PLE_PBUF_CTRL,
549+ DBG_PLE_QUEUE_EMPTY,
550+ DBG_PLE_FREEPG_CNT,
551+ DBG_PLE_FREEPG_HEAD_TAIL,
552+ DBG_PLE_PG_HIF_GROUP,
553+ DBG_PLE_HIF_PG_INFO,
554+ DBG_PLE_PG_HIF_TXCMD_GROUP,
555+ DBG_PLE_HIF_TXCMD_PG_INFO,
556+ DBG_PLE_PG_CPU_GROUP,
557+ DBG_PLE_CPU_PG_INFO,
558+ DBG_PLE_FL_QUE_CTRL,
559+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
560+ DBG_PLE_TXCMD_Q_EMPTY,
561+ DBG_PLE_AC_QEMPTY,
562+ DBG_PLE_AC_OFFSET,
563+ DBG_PLE_STATION_PAUSE,
564+ DBG_PLE_DIS_STA_MAP,
565+ DBG_PSE_PBUF_CTRL,
566+ DBG_PSE_FREEPG_CNT,
567+ DBG_PSE_FREEPG_HEAD_TAIL,
568+ DBG_PSE_HIF0_PG_INFO,
569+ DBG_PSE_PG_HIF1_GROUP,
570+ DBG_PSE_HIF1_PG_INFO,
571+ DBG_PSE_PG_CPU_GROUP,
572+ DBG_PSE_CPU_PG_INFO,
573+ DBG_PSE_PG_PLE_GROUP,
574+ DBG_PSE_PLE_PG_INFO,
575+ DBG_PSE_PG_LMAC0_GROUP,
576+ DBG_PSE_LMAC0_PG_INFO,
577+ DBG_PSE_PG_LMAC1_GROUP,
578+ DBG_PSE_LMAC1_PG_INFO,
579+ DBG_PSE_PG_LMAC2_GROUP,
580+ DBG_PSE_LMAC2_PG_INFO,
581+ DBG_PSE_PG_LMAC3_GROUP,
582+ DBG_PSE_LMAC3_PG_INFO,
583+ DBG_PSE_PG_MDP_GROUP,
584+ DBG_PSE_MDP_PG_INFO,
585+ DBG_PSE_PG_PLE1_GROUP,
586+ DBG_PSE_PLE1_PG_INFO,
587+ DBG_AGG_AALCR0,
588+ DBG_AGG_AALCR1,
589+ DBG_AGG_AALCR2,
590+ DBG_AGG_AALCR3,
591+ DBG_AGG_AALCR4,
592+ DBG_AGG_B0BRR0,
593+ DBG_AGG_B1BRR0,
594+ DBG_AGG_B2BRR0,
595+ DBG_AGG_B3BRR0,
596+ DBG_AGG_AWSCR0,
597+ DBG_AGG_PCR0,
598+ DBG_AGG_TTCR0,
599+ DBG_MIB_M0ARNG0,
600+ DBG_MIB_M0DR2,
601+ DBG_MIB_M0DR13,
developerd75d3632023-01-05 14:31:01 +0800602+ DBG_WFDMA_WED_TX_CTRL,
603+ DBG_WFDMA_WED_RX_CTRL,
developere2cc0fa2022-03-29 17:31:03 +0800604+ __MT_DBG_REG_REV_MAX,
605+};
606+
607+enum dbg_mask_rev {
608+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
609+ DBG_MIB_M0SDR14_AMPDU,
610+ DBG_MIB_M0SDR15_AMPDU_ACKED,
611+ DBG_MIB_RX_FCS_ERROR_COUNT,
612+ __MT_DBG_MASK_REV_MAX,
613+};
614+
615+enum dbg_bit_rev {
616+ __MT_DBG_BIT_REV_MAX,
617+};
618+
619+static const u32 mt7915_dbg_base[] = {
620+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
621+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
622+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
623+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
624+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
625+ [MT_DBG_SWDEF_BASE] = 0x41f200,
626+};
627+
628+static const u32 mt7916_dbg_base[] = {
629+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
630+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
631+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
632+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
633+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
634+ [MT_DBG_SWDEF_BASE] = 0x411400,
635+};
636+
637+static const u32 mt7986_dbg_base[] = {
638+ [MT_DBG_WFDMA0_BASE] = 0x24000,
639+ [MT_DBG_WFDMA1_BASE] = 0x25000,
640+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
641+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
642+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
643+ [MT_DBG_SWDEF_BASE] = 0x411400,
644+};
645+
646+/* mt7915 regs with different base and offset */
647+static const struct __dbg_reg mt7915_dbg_reg[] = {
developerd75d3632023-01-05 14:31:01 +0800648+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
649+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developere2cc0fa2022-03-29 17:31:03 +0800650+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
651+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
652+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
653+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
654+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
655+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
656+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
657+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
658+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
659+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
660+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
661+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
662+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
663+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
664+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
665+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
666+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
667+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
668+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
669+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
670+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
671+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
672+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
673+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
674+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
675+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
676+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
677+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
678+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
679+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
680+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
681+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
682+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
683+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
684+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
685+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
686+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
687+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
688+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
689+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
690+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
691+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
692+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
693+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
694+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
695+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
696+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
697+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
698+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
699+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
700+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
701+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
702+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
703+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
704+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
705+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
706+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
707+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
708+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
709+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
710+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
711+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
712+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developer94dd8d72022-05-04 17:14:16 +0800713+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developere2cc0fa2022-03-29 17:31:03 +0800714+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
715+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
716+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
717+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
718+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
719+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
720+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
721+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
722+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
723+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
724+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
725+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
726+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
727+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
728+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
729+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
730+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
731+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
732+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
733+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
734+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
735+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
736+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
737+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
738+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
739+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
740+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
741+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
742+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
743+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
744+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
745+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
746+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
747+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
748+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
749+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
750+};
751+
752+/* mt7986/mt7916 regs with different base and offset */
753+static const struct __dbg_reg mt7916_dbg_reg[] = {
developerd75d3632023-01-05 14:31:01 +0800754+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
755+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developere2cc0fa2022-03-29 17:31:03 +0800756+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
757+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
758+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
759+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
760+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
761+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
762+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
763+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
764+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
765+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
766+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
767+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
768+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
769+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
770+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
771+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
772+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
773+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
774+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
775+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
776+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
777+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
778+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
779+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
780+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
781+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
782+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
783+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
784+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
785+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
786+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
787+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
788+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
789+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
790+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
791+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
792+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
793+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
794+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
795+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
796+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
797+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
798+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
799+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
800+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
801+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
802+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
803+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
804+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
805+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
806+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
807+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
808+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
809+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
810+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
811+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
812+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
813+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developer68e1eb22022-05-09 17:02:12 +0800814+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developere2cc0fa2022-03-29 17:31:03 +0800815+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
816+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
817+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
818+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
819+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
820+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
821+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
822+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
823+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
824+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
825+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
826+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
827+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
828+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
829+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
830+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
831+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
832+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
833+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
834+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
835+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
836+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
837+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
838+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
839+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
840+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
841+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
842+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
843+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
844+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
845+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
846+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
847+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
848+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
849+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
850+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
851+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
852+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
853+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
854+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
855+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
856+};
857+
858+static const struct __dbg_mask mt7915_dbg_mask[] = {
859+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
860+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
861+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
862+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
863+};
864+
865+static const struct __dbg_mask mt7916_dbg_mask[] = {
866+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
867+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
868+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
869+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
870+};
871+
872+/* used to differentiate between generations */
873+struct mt7915_dbg_reg_desc {
874+ const u32 id;
875+ const u32 *base_rev;
876+ const struct __dbg_reg *reg_rev;
877+ const struct __dbg_mask *mask_rev;
878+};
879+
880+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
881+ { 0x7915,
882+ mt7915_dbg_base,
883+ mt7915_dbg_reg,
884+ mt7915_dbg_mask
885+ },
886+ { 0x7906,
887+ mt7916_dbg_base,
888+ mt7916_dbg_reg,
889+ mt7916_dbg_mask
890+ },
891+ { 0x7986,
892+ mt7986_dbg_base,
893+ mt7916_dbg_reg,
894+ mt7916_dbg_mask
895+ },
896+};
897+
898+struct bin_debug_hdr {
899+ __le32 magic_num;
900+ __le16 serial_id;
901+ __le16 msg_type;
902+ __le16 len;
903+ __le16 des_len; /* descriptor len for rxd */
904+} __packed;
905+
developer2324aa22023-04-12 11:30:15 +0800906+/* fw wm info related strcture */
907+struct cos_msg_trace_t {
908+ u32 dest_id;
909+ u8 msg_id;
910+ u32 pcount;
911+ u32 qread;
912+ u32 ts_enq;
913+ u32 ts_deq;
914+ u32 ts_finshq;
915+};
916+
917+struct cos_task_info_struct {
918+ u32 task_name_ptr;
919+ u32 task_qname_ptr;
920+ u32 task_priority;
921+ u16 task_stack_size;
922+ u8 task_ext_qsize;
923+ u32 task_id;
924+ u32 task_ext_qid;
925+ u32 task_main_func;
926+ u32 task_init_func;
927+};
928+
929+struct cos_program_trace_t{
930+ u32 dest_id;
931+ u32 msg_id;
932+ u32 msg_sn;
933+ u32 ts_gpt2;
934+ u32 LP;
935+ char name[12];
936+} ;
937+
938+struct cos_msg_type {
939+ u32 finish_cnt;
940+ u32 exe_time;
941+ u32 exe_peak;
942+};
943+
944+struct cos_task_type{
945+ u32 tc_stack_start;
946+ u32 tc_stack_end;
947+ u32 tc_stack_pointer;
948+ u32 tc_stack_size;
949+ u32 tc_schedule_count;
950+ u8 tc_status;
951+ u8 tc_priority;
952+ u8 tc_weight;
953+ u8 RSVD[28];
954+ u32 tc_entry_func;
955+ u32 tc_exe_start;
956+ u32 tc_exe_time;
957+ u32 tc_exe_peak;
958+ u32 tc_pcount;
959+};
960+
developere2cc0fa2022-03-29 17:31:03 +0800961+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
962+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
963+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
964+
965+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
966+ (_dev)->dbg_reg->mask_rev[(id)].start)
967+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
968+ __DBG_REG_OFFS((_dev), (id)))
969+
970+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
971+ dev->dbg_reg->mask_rev[(id)].start)
972+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
973+ __DBG_MASK(dev, (id)))
974+
975+
976+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
977+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
978+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
979+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developerd75d3632023-01-05 14:31:01 +0800980+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
981+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developere2cc0fa2022-03-29 17:31:03 +0800982+
983+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
984+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
985+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
986+
developerd75d3632023-01-05 14:31:01 +0800987+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
988+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developere2cc0fa2022-03-29 17:31:03 +0800989+/* WFDMA COMMON */
990+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
991+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
992+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
993+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
994+
995+/* WFDMA0 */
996+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
997+
998+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
999+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
1000+
1001+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
1002+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
1003+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
1004+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
1005+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
1006+
1007+
1008+/* WFDMA1 */
1009+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
1010+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
1011+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
1012+
1013+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
1014+
1015+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
1016+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
1017+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
1018+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
1019+
1020+/* WFDMA0 PCIE1 */
1021+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
1022+
1023+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
1024+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
1025+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
1026+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
1027+
1028+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1029+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1030+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1031+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1032+
1033+/* WFDMA1 PCIE1 */
1034+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
1035+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
1036+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
1037+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
1038+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
1039+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
1040+
1041+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1042+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1043+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1044+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1045+
1046+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
1047+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
1048+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
1049+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
1050+
1051+
1052+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
1053+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
1054+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
1055+
1056+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
1057+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
1058+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
1059+
1060+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
1061+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
1062+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
1063+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
1064+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
1065+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
1066+
1067+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
1068+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
1069+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
1070+
1071+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
1072+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
1073+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
1074+
1075+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
1076+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
1077+
1078+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
1079+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
1080+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
1081+
1082+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
1083+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
1084+
1085+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
1086+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
1087+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
1088+
1089+
1090+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1091+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1092+
1093+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1094+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1095+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1096+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1097+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1098+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1099+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1100+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1101+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1102+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1103+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1104+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1105+
1106+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1107+
1108+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1109+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1110+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1111+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1112+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1113+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1114+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1115+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1116+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1117+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1118+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1119+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1120+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1121+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1122+
1123+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1124+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1125+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1126+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1127+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1128+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1129+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1130+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1131+
1132+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1133+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1134+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1135+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1136+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1137+
1138+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1139+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1140+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1141+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1142+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1143+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1144+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1145+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1146+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1147+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1148+
1149+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1150+
1151+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1152+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1153+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1154+
developer8db25e72022-09-30 15:25:13 +08001155+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developere2cc0fa2022-03-29 17:31:03 +08001156+
1157+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1158+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1159+
1160+
1161+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1162+#define MT_DBG_WTBL_BASE 0x820D8000
1163+
1164+/* PLE related CRs. */
1165+#define MT_DBG_PLE_BASE 0x820C0000
1166+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1167+
1168+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1169+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1170+
1171+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1172+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1173+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1174+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1175+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1176+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1177+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1178+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1179+
1180+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1181+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1182+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1183+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1184+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1185+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1186+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1187+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1188+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1189+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1190+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1191+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1192+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1193+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1194+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1195+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1196+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1197+
1198+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1199+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1200+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1201+
1202+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1203+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1204+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1205+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1206+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1207+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1208+
1209+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1210+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1211+
1212+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1213+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1214+
1215+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1216+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1217+
1218+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1219+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1220+
1221+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1222+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1223+
1224+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1225+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1226+
1227+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1228+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1229+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1230+
1231+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1232+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1233+
1234+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1235+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1236+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1237+
1238+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1239+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1240+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1241+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1242+
1243+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1244+
1245+/* pseinfo related CRs. */
1246+#define MT_DBG_PSE_BASE 0x820C8000
1247+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1248+
developer94dd8d72022-05-04 17:14:16 +08001249+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1250+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1251+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1252+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1253+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1254+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1255+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1256+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1257+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1258+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1259+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1260+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1261+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1262+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1263+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1264+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1265+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1266+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1267+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1268+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1269+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1270+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1271+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1272+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developere2cc0fa2022-03-29 17:31:03 +08001273+
1274+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1275+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1276+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1277+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1278+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1279+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1280+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1281+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1282+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1283+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1284+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1285+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1286+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1287+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1288+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1289+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1290+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1291+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1292+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1293+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1294+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1295+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1296+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1297+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1298+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1299+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1300+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1301+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1302+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1303+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1304+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1305+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1306+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1307+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1308+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1309+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1310+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1311+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1312+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1313+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1314+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1315+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1316+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1317+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1318+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1319+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1320+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1321+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1322+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1323+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1324+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1325+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1326+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1327+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1328+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1329+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1330+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1331+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1332+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1333+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1334+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1335+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1336+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1337+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1338+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1339+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1340+
1341+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1342+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1343+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1344+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1345+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1346+
1347+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1348+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1349+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1350+
1351+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1352+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1353+
1354+
1355+/* AGG */
1356+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1357+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1358+
1359+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1360+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1361+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1362+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1363+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1364+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1365+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1366+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1367+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1368+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1369+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1370+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1371+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1372+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1373+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1374+
1375+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1376+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1377+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1378+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1379+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1380+
1381+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1382+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1383+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1384+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1385+
1386+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1387+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1388+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1389+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1390+
1391+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1392+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1393+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1394+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1395+
1396+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1397+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1398+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1399+
1400+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1401+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1402+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1403+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1404+
1405+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1406+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1407+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1408+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1409+
1410+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1411+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1412+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1413+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1414+
1415+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1416+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1417+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1418+
1419+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1420+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1421+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1422+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1423+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1424+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1425+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1426+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1427+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1428+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1429+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1430+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1431+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1432+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1433+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1434+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1435+
1436+/* mt7915 host DMA*/
1437+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1438+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1439+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1440+
1441+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1442+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1443+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1444+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1445+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1446+
1447+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1448+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1449+
1450+/* mt7986 host DMA */
1451+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1452+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1453+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1454+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1455+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1456+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1457+
1458+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1459+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1460+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1461+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1462+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1463+
1464+/* MCU DMA */
1465+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1466+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1467+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1468+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1469+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1470+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1471+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1472+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1473+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1474+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1475+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1476+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1477+
1478+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1479+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1480+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1481+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1482+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1483+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1484+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1485+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1486+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1487+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1488+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1489+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1490+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1491+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1492+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1493+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1494+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1495+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1496+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1497+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1498+
1499+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1500+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1501+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1502+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1503+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1504+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1505+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1506+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1507+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1508+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1509+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1510+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1511+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1512+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1513+
1514+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1515+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1516+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1517+/* mt7986 add */
1518+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1519+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1520+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1521+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1522+
1523+
1524+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1525+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1526+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1527+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1528+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1529+
1530+/* mt7986 add */
1531+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1532+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1533+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1534+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1535+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1536+
1537+/* MEM DMA */
1538+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1539+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1540+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1541+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1542+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1543+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1544+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1545+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1546+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1547+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1548+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1549+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1550+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1551+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1552+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1553+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1554+
1555+enum resource_attr {
1556+ HIF_TX_DATA,
1557+ HIF_TX_CMD,
1558+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1559+ HIF_TX_FWDL,
1560+ HIF_RX_DATA,
1561+ HIF_RX_EVENT,
1562+ RING_ATTR_NUM
1563+};
1564+
1565+struct hif_pci_tx_ring_desc {
1566+ u32 hw_int_mask;
1567+ u16 ring_size;
1568+ enum resource_attr ring_attr;
1569+ u8 band_idx;
1570+ char *const ring_info;
1571+};
1572+
1573+struct hif_pci_rx_ring_desc {
1574+ u32 hw_desc_base;
1575+ u32 hw_int_mask;
1576+ u16 ring_size;
1577+ enum resource_attr ring_attr;
1578+ u16 max_rx_process_cnt;
1579+ u16 max_sw_read_idx_inc;
1580+ char *const ring_info;
developerd75d3632023-01-05 14:31:01 +08001581+ bool flags;
developere2cc0fa2022-03-29 17:31:03 +08001582+};
1583+
1584+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1585+ {
1586+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1587+ .ring_size = 128,
1588+ .ring_attr = HIF_TX_FWDL,
1589+ .ring_info = "FWDL"
1590+ },
1591+ {
1592+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1593+ .ring_size = 256,
1594+ .ring_attr = HIF_TX_CMD_WM,
1595+ .ring_info = "cmd to WM"
1596+ },
1597+ {
1598+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1599+ .ring_size = 2048,
1600+ .ring_attr = HIF_TX_DATA,
1601+ .ring_info = "band0 TXD"
1602+ },
1603+ {
1604+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1605+ .ring_size = 2048,
1606+ .ring_attr = HIF_TX_DATA,
1607+ .ring_info = "band1 TXD"
1608+ },
1609+ {
1610+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1611+ .ring_size = 256,
1612+ .ring_attr = HIF_TX_CMD,
1613+ .ring_info = "cmd to WA"
1614+ }
1615+};
1616+
1617+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1618+ {
1619+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1620+ .ring_size = 1536,
1621+ .ring_attr = HIF_RX_DATA,
1622+ .ring_info = "band0 RX data"
1623+ },
1624+ {
1625+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1626+ .ring_size = 1536,
1627+ .ring_attr = HIF_RX_DATA,
1628+ .ring_info = "band1 RX data"
1629+ },
1630+ {
1631+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1632+ .ring_size = 512,
1633+ .ring_attr = HIF_RX_EVENT,
1634+ .ring_info = "event from WM"
1635+ },
1636+ {
1637+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1638+ .ring_size = 1024,
1639+ .ring_attr = HIF_RX_EVENT,
developerd75d3632023-01-05 14:31:01 +08001640+ .ring_info = "event from WA band0",
1641+ .flags = true
developere2cc0fa2022-03-29 17:31:03 +08001642+ },
1643+ {
1644+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1645+ .ring_size = 512,
1646+ .ring_attr = HIF_RX_EVENT,
1647+ .ring_info = "event from WA band1"
1648+ }
1649+};
1650+
1651+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1652+ {
1653+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1654+ .ring_size = 128,
1655+ .ring_attr = HIF_TX_FWDL,
1656+ .ring_info = "FWDL"
1657+ },
1658+ {
1659+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1660+ .ring_size = 256,
1661+ .ring_attr = HIF_TX_CMD_WM,
1662+ .ring_info = "cmd to WM"
1663+ },
1664+ {
1665+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1666+ .ring_size = 2048,
1667+ .ring_attr = HIF_TX_DATA,
1668+ .ring_info = "band0 TXD"
1669+ },
1670+ {
1671+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1672+ .ring_size = 2048,
1673+ .ring_attr = HIF_TX_DATA,
1674+ .ring_info = "band1 TXD"
1675+ },
1676+ {
1677+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1678+ .ring_size = 256,
1679+ .ring_attr = HIF_TX_CMD,
1680+ .ring_info = "cmd to WA"
1681+ }
1682+};
1683+
1684+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1685+ {
1686+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1687+ .ring_size = 1536,
1688+ .ring_attr = HIF_RX_DATA,
1689+ .ring_info = "band0 RX data"
1690+ },
1691+ {
1692+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1693+ .ring_size = 1536,
1694+ .ring_attr = HIF_RX_DATA,
1695+ .ring_info = "band1 RX data"
1696+ },
1697+ {
1698+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1699+ .ring_size = 512,
1700+ .ring_attr = HIF_RX_EVENT,
1701+ .ring_info = "event from WM"
1702+ },
1703+ {
1704+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1705+ .ring_size = 512,
1706+ .ring_attr = HIF_RX_EVENT,
1707+ .ring_info = "event from WA"
1708+ },
1709+ {
1710+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1711+ .ring_size = 1024,
1712+ .ring_attr = HIF_RX_EVENT,
developerd75d3632023-01-05 14:31:01 +08001713+ .ring_info = "STS WA band0",
1714+ .flags = true
developere2cc0fa2022-03-29 17:31:03 +08001715+ },
1716+ {
1717+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1718+ .ring_size = 512,
1719+ .ring_attr = HIF_RX_EVENT,
1720+ .ring_info = "STS WA band1"
1721+ },
1722+};
1723+
1724+/* mibinfo related CRs. */
1725+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1726+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1727+
1728+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1729+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1730+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1731+
1732+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1733+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1734+
1735+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1736+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1737+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1738+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1739+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1740+
1741+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1742+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1743+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1744+
1745+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1746+
1747+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1748+
1749+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1750+
1751+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1752+
1753+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1754+
1755+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1756+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1757+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1758+
1759+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1760+
1761+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1762+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1763+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1764+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1765+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1766+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1767+
1768+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1769+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1770+
1771+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1772+
1773+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1774+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1775+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1776+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1777+
1778+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1779+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1780+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1781+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1782+
1783+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1784+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1785+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1786+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1787+
1788+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1789+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1790+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1791+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1792+
1793+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1794+
1795+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1796+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1797+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1798+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1799+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1800+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1801+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1802+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1803+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1804+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1805+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1806+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1807+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1808+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1809+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1810+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1811+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1812+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1813+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1814+
1815+
1816+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1817+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1818+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1819+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1820+
1821+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1822+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1823+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1824+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1825+
1826+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1827+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1828+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1829+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1830+
1831+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1832+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1833+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1834+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1835+
1836+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1837+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1838+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1839+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1840+
1841+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1842+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1843+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1844+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1845+
1846+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1847+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1848+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1849+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1850+
1851+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1852+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1853+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1854+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1855+
1856+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1857+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1858+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1859+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1860+
1861+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1862+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1863+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1864+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1865+
1866+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1867+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1868+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1869+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1870+/* TXD */
1871+
1872+#define MT_TXD1_ETYP BIT(15)
1873+#define MT_TXD1_VLAN BIT(14)
1874+#define MT_TXD1_RMVL BIT(13)
1875+#define MT_TXD1_AMS BIT(13)
1876+#define MT_TXD1_EOSP BIT(12)
1877+#define MT_TXD1_MRD BIT(11)
1878+
1879+#define MT_TXD7_CTXD BIT(26)
1880+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1881+#define MT_TXD7_TAT GENMASK(9, 0)
1882+
1883+#endif
1884+#endif
1885diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1886new file mode 100644
developerab4a0b82023-08-18 19:56:34 +08001887index 00000000..275acc61
developere2cc0fa2022-03-29 17:31:03 +08001888--- /dev/null
1889+++ b/mt7915/mtk_debugfs.c
developerab4a0b82023-08-18 19:56:34 +08001890@@ -0,0 +1,3622 @@
developere2cc0fa2022-03-29 17:31:03 +08001891+#include<linux/inet.h>
1892+#include "mt7915.h"
1893+#include "mt7915_debug.h"
1894+#include "mac.h"
1895+#include "mcu.h"
1896+
1897+#ifdef MTK_DEBUG
1898+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1899+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1900+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1901+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1902+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1903+
1904+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1905+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1906+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1907+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1908+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1909+
1910+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1911+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1912+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1913+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1914+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1915+
1916+enum mt7915_wtbl_type {
1917+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1918+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1919+ WTBL_TYPE_KEY, /* Key Table */
1920+ MAX_NUM_WTBL_TYPE
1921+};
1922+
1923+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1924+ enum mt7915_wtbl_type type, u16 start_dw,
1925+ u16 len, void *buf)
1926+{
1927+ u32 *dest_cpy = (u32 *)buf;
1928+ u32 size_dw = len;
1929+ u32 src = 0;
1930+
1931+ if (!buf)
1932+ return 0xFF;
1933+
1934+ if (type == WTBL_TYPE_LMAC) {
1935+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1936+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1937+ src = LWTBL_IDX2BASE(idx, start_dw);
1938+ } else if (type == WTBL_TYPE_UMAC) {
1939+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1940+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1941+ src = UWTBL_IDX2BASE(idx, start_dw);
1942+ } else if (type == WTBL_TYPE_KEY) {
1943+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1944+ MT_UWTBL_TOP_WDUCR_TARGET |
1945+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1946+ src = KEYTBL_IDX2BASE(idx, start_dw);
1947+ }
1948+
1949+ while (size_dw--) {
1950+ *dest_cpy++ = mt76_rr(dev, src);
1951+ src += 4;
1952+ };
1953+
1954+ return 0;
1955+}
1956+
1957+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1958+ enum mt7915_wtbl_type type, u16 start_dw,
1959+ u32 val)
1960+{
1961+ u32 addr = 0;
1962+
1963+ if (type == WTBL_TYPE_LMAC) {
1964+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1965+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1966+ addr = LWTBL_IDX2BASE(idx, start_dw);
1967+ } else if (type == WTBL_TYPE_UMAC) {
1968+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1969+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1970+ addr = UWTBL_IDX2BASE(idx, start_dw);
1971+ } else if (type == WTBL_TYPE_KEY) {
1972+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1973+ MT_UWTBL_TOP_WDUCR_TARGET |
1974+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1975+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1976+ }
1977+
1978+ mt76_wr(dev, addr, val);
1979+
1980+ return 0;
1981+}
1982+
1983+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1984+{
1985+ struct bin_debug_hdr *hdr;
1986+ char *buf;
1987+
1988+ if (len > 1500 - sizeof(*hdr))
1989+ len = 1500 - sizeof(*hdr);
1990+
1991+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1992+ if (!buf)
1993+ return;
1994+
1995+ hdr = (struct bin_debug_hdr *)buf;
1996+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1997+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1998+ hdr->msg_type = cpu_to_le16(type);
1999+ hdr->len = cpu_to_le16(len);
2000+ hdr->des_len = cpu_to_le16(des_len);
2001+
2002+ memcpy(buf + sizeof(*hdr), data, len);
2003+
2004+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
2005+}
2006+
2007+static int
2008+mt7915_fw_debug_module_set(void *data, u64 module)
2009+{
2010+ struct mt7915_dev *dev = data;
2011+
2012+ dev->dbg.fw_dbg_module = module;
2013+ return 0;
2014+}
2015+
2016+static int
2017+mt7915_fw_debug_module_get(void *data, u64 *module)
2018+{
2019+ struct mt7915_dev *dev = data;
2020+
2021+ *module = dev->dbg.fw_dbg_module;
2022+ return 0;
2023+}
2024+
2025+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
2026+ mt7915_fw_debug_module_set, "%lld\n");
2027+
2028+static int
2029+mt7915_fw_debug_level_set(void *data, u64 level)
2030+{
2031+ struct mt7915_dev *dev = data;
2032+
2033+ dev->dbg.fw_dbg_lv = level;
2034+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2035+ return 0;
2036+}
2037+
2038+static int
2039+mt7915_fw_debug_level_get(void *data, u64 *level)
2040+{
2041+ struct mt7915_dev *dev = data;
2042+
2043+ *level = dev->dbg.fw_dbg_lv;
2044+ return 0;
2045+}
2046+
2047+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
2048+ mt7915_fw_debug_level_set, "%lld\n");
2049+
2050+#define MAX_TX_MODE 12
2051+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
2052+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
2053+ "HE_TRIG", "HE_MU", "N/A"};
2054+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
2055+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
2056+ "N/A"};
2057+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
2058+ "48M", "54M", "N/A"};
2059+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
2060+ "20/40/80/160/80+80MHz"};
2061+
2062+static char *hw_rate_ofdm_str(u16 ofdm_idx)
2063+{
2064+ switch (ofdm_idx) {
2065+ case 11: /* 6M */
2066+ return HW_TX_RATE_OFDM_STR[0];
2067+
2068+ case 15: /* 9M */
2069+ return HW_TX_RATE_OFDM_STR[1];
2070+
2071+ case 10: /* 12M */
2072+ return HW_TX_RATE_OFDM_STR[2];
2073+
2074+ case 14: /* 18M */
2075+ return HW_TX_RATE_OFDM_STR[3];
2076+
2077+ case 9: /* 24M */
2078+ return HW_TX_RATE_OFDM_STR[4];
2079+
2080+ case 13: /* 36M */
2081+ return HW_TX_RATE_OFDM_STR[5];
2082+
2083+ case 8: /* 48M */
2084+ return HW_TX_RATE_OFDM_STR[6];
2085+
2086+ case 12: /* 54M */
2087+ return HW_TX_RATE_OFDM_STR[7];
2088+
2089+ default:
2090+ return HW_TX_RATE_OFDM_STR[8];
2091+ }
2092+}
2093+
2094+static char *hw_rate_str(u8 mode, u16 rate_idx)
2095+{
2096+ if (mode == 0)
2097+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2098+ else if (mode == 1)
2099+ return hw_rate_ofdm_str(rate_idx);
2100+ else
2101+ return "MCS";
2102+}
2103+
2104+static void parse_rate(struct seq_file *s, u16 rate_i