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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 1a42537ea87b28fb84806cf0efa4accf1bbf3059 / . / target / linux / mediatek / files-5.4 / drivers / clk / mediatek / clk-mt7988.c
blob: 9520ab8abbba6beebc07340da83237d289623bc5 [file] [log] [blame]
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1/*
2 * Copyright (c) 2022 MediaTek Inc.
3 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/mfd/syscon.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/mfd/syscon.h>
24
25#include "clk-mtk.h"
26#include "clk-gate.h"
27#include "clk-mux.h"
28
29#include <dt-bindings/clock/mt7988-clk.h>
30
31static DEFINE_SPINLOCK(mt7988_clk_lock);
32
33static const struct mtk_fixed_factor top_divs[] __initconst = {
34 FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
35 FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
36 FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
37 FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
38 FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
39 FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
40 FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
41 FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
42 FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
43 FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
44 FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
45 FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
46 FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
47 FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
48 FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", "apll2", 1, 4),
49 FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
50 FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
51 FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
52 FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
53 FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
54 FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
55 FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
56 FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", "net1pll", 1, 64),
57 FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", "net1pll", 1, 128),
58 FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
59 FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
60 FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
61 FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
62 FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", "net2pll", 1, 32),
63 FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
64 FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", "net2pll", 1, 8),
65 FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
66 FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
67 FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", "netsyspll", 1, 1),
68 FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", "msdcpll", 1, 1),
69 FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
70 FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
71 FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
72 FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", "cb_rtc_32p7k", 1, 1),
73 FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", "clkxtal", 1, 1),
74 FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
75 FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", "netsys_gsw_sel", 1, 1),
76 FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
77 FACTOR(CK_TOP_EIP197, "eip197", "eip197_sel", 1, 1),
78 FACTOR(CK_TOP_EMMC_250M, "emmc_250m", "emmc_250m_sel", 1, 1),
79 FACTOR(CK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
80 FACTOR(CK_TOP_SPI, "spi", "spi_sel", 1, 1),
81 FACTOR(CK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
82 FACTOR(CK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
83 FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
84 FACTOR(CK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
85 FACTOR(CK_TOP_USB_SYS, "usb_sys", "usb_sys_sel", 1, 1),
86 FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", "usb_sys_p1_sel", 1, 1),
87 FACTOR(CK_TOP_USB_XHCI, "usb_xhci", "usb_xhci_sel", 1, 1),
88 FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", "usb_xhci_p1_sel", 1, 1),
89 FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
90 FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", "usb_frmcnt_p1_sel", 1,
91 1),
92 FACTOR(CK_TOP_AUD, "aud", "aud_sel", 1, 1),
93 FACTOR(CK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
94 FACTOR(CK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
95 FACTOR(CK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
96 FACTOR(CK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
97 FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", "csw_infra_f26m_sel", 1, 1),
98 FACTOR(CK_TOP_USB_REF, "usb_ref", "cksq_src", 1, 1),
99 FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", "cksq_src", 1, 1),
100};
101
102static const struct mtk_fixed_factor infra_divs[] __initconst = {
103 FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", "csw_infra_f26m_sel", 1, 1),
104 FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", "pwm_sel", 1, 1),
105 FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", "pextp_tl_ck_sel",
106 1, 1),
107 FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
108 "pextp_tl_ck_p1_sel", 1, 1),
109 FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
110 "pextp_tl_ck_p2_sel", 1, 1),
111 FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
112 "pextp_tl_ck_p3_sel", 1, 1),
113 FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1),
114 FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", "infra_133m_hck", 1, 1),
115 FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1),
116 FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", "aud_l", 1, 1),
117 FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", "a1sys", 1, 1),
118 FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", "a_tuner", 1, 1),
119 FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", "i2c_bck", 1, 1),
120 FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", "uart_sel", 1, 1),
121 FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", "uart_sel", 1, 1),
122 FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", "uart_sel", 1, 1),
123 FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", "nfi1x", 1, 1),
124 FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", "spinfi_bck", 1, 1),
125 FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", "spi", 1, 1),
126 FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", "spim_mst", 1, 1),
127 FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", "infra_frtc", 1, 1),
128 FACTOR(CK_INFRA_FRTC, "infra_frtc", "cb_rtc_32k", 1, 1),
129 FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", "emmc_400m", 1, 1),
130 FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", "emmc_250m", 1,
131 1),
132 FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1),
133 FACTOR(CK_INFRA_USB_O, "infra_usb_o", "usb_ref", 1, 1),
134 FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", "usb_ck_p1", 1, 1),
135 FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", "usb_frmcnt", 1, 1),
136 FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
137 "usb_frmcnt_p1", 1, 1),
138 FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", "usb_xhci", 1, 1),
139 FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", "usb_xhci_p1", 1,
140 1),
developer1a425372023-03-31 15:47:21 +0800[diff] [blame^]141 FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "sspxtp_sel", 1, 1),
142 FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "usb_phy_sel", 1,
143 1),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]144 FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", "clkxtal", 1, 1),
145 FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", "clkxtal", 1, 1),
146 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
147 "clkxtal", 1, 1),
148 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
149 "clkxtal", 1, 1),
150 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
151 "clkxtal", 1, 1),
152 FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
153 "clkxtal", 1, 1),
154 FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", "csw_infra_f26m", 1, 1),
155 FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", "csw_infra_f26m", 1, 1),
156 FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", "sysaxi", 1, 1),
157 FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi", 1, 1),
158 FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", "sysaxi", 1, 1),
159 FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", "usb_sys", 1, 1),
160 FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", "usb_sys_p1", 1, 1),
161};
162
163static const char *const mcu_bus_div_parents[] = { "cb_cksq_40m", "ccipll2_b",
164 "cb_net1_d4" };
165
166static const char *const mcu_arm_div_parents[] = { "cb_cksq_40m", "arm_b",
167 "cb_net1_d4" };
168
169static struct mtk_composite mcu_muxes[] = {
170 /* bus_pll_divider_cfg */
171 MUX_GATE_FLAGS(CK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
172 mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
173 /* mp2_pll_divider_cfg */
174 MUX_GATE_FLAGS(CK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
175 mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
176};
177
178static const char *const netsys_parents[] = { "cb_cksq_40m", "cb_net2_d2",
179 "cb_mm_d2" };
180
181static const char *const netsys_500m_parents[] = { "cb_cksq_40m", "cb_net1_d5",
182 "net1_d5_d2" };
183
184static const char *const netsys_2x_parents[] = { "cb_cksq_40m", "cb_net2_800m",
185 "cb_mm_720m" };
186
187static const char *const netsys_gsw_parents[] = { "cb_cksq_40m", "cb_net1_d4",
188 "cb_net1_d5" };
189
190static const char *const eth_gmii_parents[] = { "cb_cksq_40m", "net1_d5_d4" };
191
192static const char *const netsys_mcu_parents[] = { "cb_cksq_40m", "cb_net2_800m",
193 "cb_mm_720m", "cb_net1_d4",
194 "cb_net1_d5", "cb_m_416m" };
195
196static const char *const eip197_parents[] = { "cb_cksq_40m", "cb_netsys_850m",
197 "cb_net2_800m", "cb_mm_720m",
198 "cb_net1_d4", "cb_net1_d5" };
199
200static const char *const axi_infra_parents[] = { "cb_cksq_40m", "net1_d8_d2" };
201
202static const char *const uart_parents[] = { "cb_cksq_40m", "cb_m_d8",
203 "m_d8_d2" };
204
205static const char *const emmc_250m_parents[] = { "cb_cksq_40m", "net1_d5_d2",
206 "cb_mm_d4" };
207
208static const char *const emmc_400m_parents[] = { "cb_cksq_40m", "cb_msdc_400m",
209 "cb_mm_d2", "cb_m_d2",
210 "cb_mm_d4", "net1_d8_d2" };
211
212static const char *const spi_parents[] = { "cb_cksq_40m", "cb_m_d2",
213 "cb_mm_d4", "net1_d8_d2",
214 "cb_net2_d6", "net1_d5_d4",
215 "cb_m_d4", "net1_d8_d4" };
216
217static const char *const nfi1x_parents[] = { "cb_cksq_40m", "cb_mm_d4",
218 "net1_d8_d2", "cb_net2_d6",
219 "cb_m_d4", "cb_mm_d8",
220 "net1_d8_d4", "cb_m_d8" };
221
222static const char *const spinfi_parents[] = { "cksq_40m_d2", "cb_cksq_40m",
223 "net1_d5_d4", "cb_m_d4",
224 "cb_mm_d8", "net1_d8_d4",
225 "mm_d6_d2", "cb_m_d8" };
226
227static const char *const pwm_parents[] = { "cb_cksq_40m", "net1_d8_d2",
228 "net1_d5_d4", "cb_m_d4",
229 "m_d8_d2", "cb_rtc_32k" };
230
231static const char *const i2c_parents[] = { "cb_cksq_40m", "net1_d5_d4",
232 "cb_m_d4", "net1_d8_d4" };
233
234static const char *const pcie_mbist_250m_parents[] = { "cb_cksq_40m",
235 "net1_d5_d2" };
236
237static const char *const pextp_tl_ck_parents[] = { "cb_cksq_40m", "cb_net2_d6",
238 "cb_mm_d8", "m_d8_d2",
239 "cb_rtc_32k" };
240
241static const char *const usb_frmcnt_parents[] = { "cb_cksq_40m",
242 "cb_mm_d3_d5" };
243
244static const char *const aud_parents[] = { "cb_cksq_40m", "cb_apll2_196m" };
245
246static const char *const a1sys_parents[] = { "cb_cksq_40m", "cb_apll2_d4" };
247
248static const char *const aud_l_parents[] = { "cb_cksq_40m", "cb_apll2_196m",
249 "m_d8_d2" };
250
251static const char *const sspxtp_parents[] = { "cksq_40m_d2", "m_d8_d2" };
252
253static const char *const usxgmii_sbus_0_parents[] = { "cb_cksq_40m",
254 "net1_d8_d4" };
255
256static const char *const sgm_0_parents[] = { "cb_cksq_40m", "cb_sgm_325m" };
257
258static const char *const sysapb_parents[] = { "cb_cksq_40m", "m_d3_d2" };
259
260static const char *const eth_refck_50m_parents[] = { "cb_cksq_40m",
261 "net2_d4_d4" };
262
263static const char *const eth_sys_200m_parents[] = { "cb_cksq_40m",
264 "cb_net2_d4" };
265
266static const char *const eth_xgmii_parents[] = { "cksq_40m_d2", "net1_d8_d8",
267 "net1_d8_d16" };
268
269static const char *const bus_tops_parents[] = { "cb_cksq_40m", "cb_net1_d5",
270 "cb_net2_d2" };
271
272static const char *const npu_tops_parents[] = { "cb_cksq_40m", "cb_net2_800m" };
273
274static const char *const dramc_md32_parents[] = { "cb_cksq_40m", "cb_m_d2",
275 "cb_wedmcu_208m" };
276
277static const char *const da_xtp_glb_p0_parents[] = { "cb_cksq_40m",
278 "cb_net2_d8" };
279
280static const char *const mcusys_backup_625m_parents[] = { "cb_cksq_40m",
281 "cb_net1_d4" };
282
283static const char *const macsec_parents[] = { "cb_cksq_40m", "cb_sgm_325m",
284 "cb_net1_d8" };
285
286static const char *const netsys_tops_400m_parents[] = { "cb_cksq_40m",
287 "cb_net2_d2" };
288
289static const char *const eth_mii_parents[] = { "cksq_40m_d2", "net2_d4_d8" };
290
291static struct mtk_mux top_muxes[] = {
292 /* CLK_CFG_0 */
293 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
294 0x000, 0x004, 0x008, 0, 2, 7, 0x1C0, 0),
295 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
296 netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15,
297 0x1C0, 1),
298 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
299 netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
300 0x1C0, 2),
301 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
302 netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, 31,
303 0x1C0, 3),
304 /* CLK_CFG_1 */
305 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
306 eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
307 0x1C0, 4),
308 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
309 netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
310 0x1C0, 5),
311 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
312 netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, 23,
313 0x1C0, 6),
314 MUX_GATE_CLR_SET_UPD(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
315 0x010, 0x014, 0x018, 24, 3, 31, 0x1C0, 7),
316 /* CLK_CFG_2 */
317 MUX_GATE_CLR_SET_UPD(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
318 axi_infra_parents, 0x020, 0x024, 0x028, 0, 1, 7,
319 0x1C0, 8),
320 MUX_GATE_CLR_SET_UPD(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
321 0x024, 0x028, 8, 2, 15, 0x1C0, 9),
322 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
323 emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
324 0x1C0, 10),
325 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
326 emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
327 0x1C0, 11),
328 /* CLK_CFG_3 */
329 MUX_GATE_CLR_SET_UPD(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
330 0x034, 0x038, 0, 3, 7, 0x1C0, 12),
331 MUX_GATE_CLR_SET_UPD(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
332 0x030, 0x034, 0x038, 8, 3, 15, 0x1C0, 13),
333 MUX_GATE_CLR_SET_UPD(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
334 0x030, 0x034, 0x038, 16, 3, 23, 0x1C0, 14),
335 MUX_GATE_CLR_SET_UPD(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
336 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15),
337 /* CLK_CFG_4 */
338 MUX_GATE_CLR_SET_UPD(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
339 0x044, 0x048, 0, 3, 7, 0x1C0, 16),
340 MUX_GATE_CLR_SET_UPD(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
341 0x044, 0x048, 8, 2, 15, 0x1C0, 17),
342 MUX_GATE_CLR_SET_UPD(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
343 pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16,
344 1, 23, 0x1C0, 18),
345 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
346 pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
347 31, 0x1C0, 19),
348 /* CLK_CFG_5 */
349 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
350 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
351 0x1C0, 20),
352 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
353 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, 15,
354 0x1C0, 21),
355 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
356 pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
357 23, 0x1C0, 22),
358 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_SYS_SEL, "usb_sys_sel",
359 eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
360 0x1C0, 23),
361 /* CLK_CFG_6 */
362 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
363 eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
364 0x1C0, 24),
365 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
366 eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
367 0x1C0, 25),
368 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
369 eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
370 0x1C0, 26),
371 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
372 usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, 31,
373 0x1C0, 27),
374 /* CLK_CFG_7 */
375 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
376 usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
377 0x1C0, 28),
378 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
379 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
380 MUX_GATE_CLR_SET_UPD(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
381 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30),
382 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
383 0x070, 0x074, 0x078, 24, 2, 31, 0x1C4, 0),
384 /* CLK_CFG_8 */
385 MUX_GATE_CLR_SET_UPD(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
386 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
387 MUX_GATE_CLR_SET_UPD(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
388 0x080, 0x084, 0x088, 8, 1, 15, 0x1C4, 2),
389 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents,
390 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
391 MUX_GATE_CLR_SET_UPD(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
392 usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1,
393 31, 0x1C4, 4),
394 /* CLK_CFG_9 */
395 MUX_GATE_CLR_SET_UPD(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
396 usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
397 7, 0x1C4, 5),
398 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
399 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]400 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
401 usxgmii_sbus_0_parents,
402 0x090, 0x094, 0x098, 16, 1,
403 23, 0x1C4, 7, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]404 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
405 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8),
406 /* CLK_CFG_10 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]407 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
408 usxgmii_sbus_0_parents,
409 0x0A0, 0x0A4, 0x0A8, 0, 1,
410 7, 0x1C4, 9, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]411 MUX_GATE_CLR_SET_UPD(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
412 sspxtp_parents, 0x0A0, 0x0A4, 0x0A8, 8, 1, 15,
413 0x1C4, 10),
414 MUX_GATE_CLR_SET_UPD(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
415 sspxtp_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23,
416 0x1C4, 11),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]417 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAXI_SEL, "sysaxi_sel",
418 axi_infra_parents,
419 0x0A0, 0x0A4, 0x0A8, 24, 1, 31,
420 0x1C4, 12, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]421 /* CLK_CFG_11 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]422 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAPB_SEL, "sysapb_sel",
423 sysapb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 1, 7,
424 0x1C4, 13, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]425 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
426 eth_refck_50m_parents, 0x0B0, 0x0B4, 0x0B8, 8, 1,
427 15, 0x1C4, 14),
428 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
429 eth_sys_200m_parents, 0x0B0, 0x0B4, 0x0B8, 16, 1,
430 23, 0x1C4, 15),
431 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_SEL, "eth_sys_sel",
432 pcie_mbist_250m_parents, 0x0B0, 0x0B4, 0x0B8, 24,
433 1, 31, 0x1C4, 16),
434 /* CLK_CFG_12 */
435 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
436 eth_xgmii_parents, 0x0C0, 0x0C4, 0x0C8, 0, 2, 7,
437 0x1C4, 17),
438 MUX_GATE_CLR_SET_UPD(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
439 bus_tops_parents, 0x0C0, 0x0C4, 0x0C8, 8, 2, 15,
440 0x1C4, 18),
441 MUX_GATE_CLR_SET_UPD(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
442 npu_tops_parents, 0x0C0, 0x0C4, 0x0C8, 16, 1, 23,
443 0x1C4, 19),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]444 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_SEL, "dramc_sel",
445 sspxtp_parents, 0x0C0, 0x0C4, 0x0C8, 24, 1, 31,
446 0x1C4, 20, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]447 /* CLK_CFG_13 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]448 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
449 dramc_md32_parents,
450 0x0D0, 0x0D4, 0x0D8, 0, 2, 7,
451 0x1C4, 21, CLK_IS_CRITICAL),
452 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel",
453 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 8, 1, 15,
454 0x1C4, 22, CLK_IS_CRITICAL),
455 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
456 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 16, 1, 23,
457 0x1C4, 23, CLK_IS_CRITICAL),
458 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
459 sspxtp_parents, 0x0D0, 0x0D4, 0x0D8, 24, 1, 31,
460 0x1C4, 24, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]461 /* CLK_CFG_14 */
developeref309762023-01-11 15:53:46 +0800[diff] [blame]462 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
463 sspxtp_parents, 0x0E0, 0x0E4, 0x0E8, 0, 1, 7,
464 0x1C4, 25, CLK_IS_CRITICAL),
465 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
466 sspxtp_parents, 0x0E0, 0x0E4, 0x0E8, 8, 1, 15,
467 0x1C4, 26, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]468 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
469 da_xtp_glb_p0_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1,
470 23, 0x1C4, 27),
471 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
472 da_xtp_glb_p0_parents, 0x0E0, 0x0E4, 0x0E8, 24, 1,
473 31, 0x1C4, 28),
474 /* CLK_CFG_15 */
475 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
476 da_xtp_glb_p0_parents, 0x0F0, 0x0F4, 0x0F8, 0, 1,
477 7, 0x1C4, 29),
478 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
479 da_xtp_glb_p0_parents, 0x0F0, 0x0F4, 0x0F8, 8, 1,
480 15, 0x1C4, 30),
481 MUX_GATE_CLR_SET_UPD(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
482 0x0F4, 0x0F8, 16, 1, 23, 0x1C8, 0),
483 MUX_GATE_CLR_SET_UPD(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel",
484 sspxtp_parents, 0x0F0, 0x0F4, 0x0F8, 24, 1, 31,
485 0x1C8, 1),
486 /* CLK_CFG_16 */
487 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
488 0x0100, 0x104, 0x108, 0, 1, 7, 0x1C8, 2),
489 MUX_GATE_CLR_SET_UPD(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
490 sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
491 0x1C8, 3),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]492 MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_MCUSYS_BACKUP_625M_SEL,
493 "mcusys_backup_625m_sel",
494 mcusys_backup_625m_parents,
495 0x0100, 0x104, 0x108,
496 16, 1, 23, 0x1C8, 4, CLK_IS_CRITICAL),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]497 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SYNC_250M_SEL,
498 "netsys_sync_250m_sel", pcie_mbist_250m_parents,
499 0x0100, 0x104, 0x108, 24, 1, 31, 0x1C8, 5),
500 /* CLK_CFG_17 */
501 MUX_GATE_CLR_SET_UPD(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
502 0x0110, 0x114, 0x118, 0, 2, 7, 0x1C8, 6),
503 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_TOPS_400M_SEL,
504 "netsys_tops_400m_sel", netsys_tops_400m_parents,
505 0x0110, 0x114, 0x118, 8, 1, 15, 0x1C8, 7),
506 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_PPEFB_250M_SEL,
507 "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
508 0x0110, 0x114, 0x118, 16, 1, 23, 0x1C8, 8),
509 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
510 netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
511 0x1C8, 9),
512 /* CLK_CFG_18 */
513 MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents,
514 0x0120, 0x124, 0x128, 0, 1, 7, 0x1C8, 10),
515 MUX_GATE_CLR_SET_UPD(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL,
516 "ck_npu_sel_cm_tops_sel", netsys_2x_parents,
517 0x0120, 0x124, 0x128, 8, 2, 15, 0x1C8, 11),
518};
519
520static const char *const infra_mux_uart0_parents[] __initconst = {
521 "infra_ck_f26m", "infra_uart_o0"
522};
523
524static const char *const infra_mux_uart1_parents[] __initconst = {
525 "infra_ck_f26m", "infra_uart_o1"
526};
527
528static const char *const infra_mux_uart2_parents[] __initconst = {
529 "infra_ck_f26m", "infra_uart_o2"
530};
531
532static const char *const infra_mux_spi0_parents[] __initconst = {
533 "infra_i2c_o", "infra_spi0_o"
534};
535
536static const char *const infra_mux_spi1_parents[] __initconst = {
537 "infra_i2c_o", "infra_spi1_o"
538};
539
540static const char *const infra_pwm_bck_parents[] __initconst = {
541 "csw_infra_f32k", "infra_ck_f26m", "infra_66m_mck", "infra_pwm_o"
542};
543
544static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
545 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
546 "infra_pcie_ck_occ_p0"
547};
548
549static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
550 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
551 "infra_pcie_ck_occ_p1"
552};
553
554static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
555 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
556 "infra_pcie_ck_occ_p2"
557};
558
559static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
560 "csw_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
561 "infra_pcie_ck_occ_p3"
562};
563
564static const struct mtk_mux infra_muxes[] = {
565 /* MODULE_CLK_SEL_0 */
566 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
567 infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0,
568 1, -1, -1, -1),
569 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
570 infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1,
571 1, -1, -1, -1),
572 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
573 infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2,
574 1, -1, -1, -1),
575 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
576 infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
577 1, -1, -1, -1),
578 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
579 infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
580 1, -1, -1, -1),
581 MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
582 infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
583 1, -1, -1, -1),
584 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_SEL, "infra_pwm_sel",
585 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
586 2, -1, -1, -1),
587 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
588 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
589 2, -1, -1, -1),
590 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
591 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
592 2, -1, -1, -1),
593 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
594 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
595 2, -1, -1, -1),
596 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
597 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
598 2, -1, -1, -1),
599 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
600 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
601 2, -1, -1, -1),
602 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
603 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
604 2, -1, -1, -1),
605 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
606 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
607 2, -1, -1, -1),
608 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
609 infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
610 2, -1, -1, -1),
611 /* MODULE_CLK_SEL_1 */
612 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
613 "infra_pcie_gfmux_tl_o_p0_sel",
614 infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
615 0x0020, 0x0024, 0, 2, -1, -1, -1),
616 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
617 "infra_pcie_gfmux_tl_o_p1_sel",
618 infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
619 0x0020, 0x0024, 2, 2, -1, -1, -1),
620 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
621 "infra_pcie_gfmux_tl_o_p2_sel",
622 infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
623 0x0020, 0x0024, 4, 2, -1, -1, -1),
624 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
625 "infra_pcie_gfmux_tl_o_p3_sel",
626 infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
627 0x0020, 0x0024, 6, 2, -1, -1, -1),
628};
629
developer4323f7e2022-10-13 11:09:46 +0800[diff] [blame]630static struct mtk_composite top_aud_divs[] = {
631 DIV_GATE(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
632 0x0420, 0, 0x0420, 8, 8),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]633};
634
635static const struct mtk_gate_regs infra0_cg_regs = {
636 .set_ofs = 0x10,
637 .clr_ofs = 0x14,
638 .sta_ofs = 0x18,
639};
640
641static const struct mtk_gate_regs infra1_cg_regs = {
642 .set_ofs = 0x40,
643 .clr_ofs = 0x44,
644 .sta_ofs = 0x48,
645};
646
647static const struct mtk_gate_regs infra2_cg_regs = {
648 .set_ofs = 0x50,
649 .clr_ofs = 0x54,
650 .sta_ofs = 0x58,
651};
652
653static const struct mtk_gate_regs infra3_cg_regs = {
654 .set_ofs = 0x60,
655 .clr_ofs = 0x64,
656 .sta_ofs = 0x68,
657};
658
659#define GATE_INFRA0(_id, _name, _parent, _shift) \
660 { \
661 .id = _id, .name = _name, .parent_name = _parent, \
662 .regs = &infra0_cg_regs, .shift = _shift, \
663 .ops = &mtk_clk_gate_ops_setclr, \
664 }
665
666#define GATE_INFRA1(_id, _name, _parent, _shift) \
667 { \
668 .id = _id, .name = _name, .parent_name = _parent, \
669 .regs = &infra1_cg_regs, .shift = _shift, \
670 .ops = &mtk_clk_gate_ops_setclr, \
671 }
672
673#define GATE_INFRA2(_id, _name, _parent, _shift) \
674 { \
675 .id = _id, .name = _name, .parent_name = _parent, \
676 .regs = &infra2_cg_regs, .shift = _shift, \
677 .ops = &mtk_clk_gate_ops_setclr, \
678 }
679
680#define GATE_INFRA3(_id, _name, _parent, _shift) \
681 { \
682 .id = _id, .name = _name, .parent_name = _parent, \
683 .regs = &infra3_cg_regs, .shift = _shift, \
684 .ops = &mtk_clk_gate_ops_setclr, \
685 }
686
developeref309762023-01-11 15:53:46 +0800[diff] [blame]687#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \
688 .id = _id, .name = _name, .parent_name = _parent, \
689 .regs = _regs, .shift = _shift, \
690 .flags = CLK_IS_CRITICAL, \
691 .ops = &mtk_clk_gate_ops_setclr, \
692 }
693
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]694static const struct mtk_gate infra_clks[] __initconst = {
695 /* INFRA0 */
696 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
697 "infra_pcie_peri_ck_26m_ck_p0", "infra_f26m_o0", 7),
698 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
699 "infra_pcie_peri_ck_26m_ck_p1", "infra_f26m_o0", 8),
700 GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
701 "infra_pcie_peri_ck_26m_ck_p2", "infra_f26m_o0", 9),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]702 GATE_CRITICAL(CK_INFRA_PCIE_PERI_26M_CK_P3,
703 "infra_pcie_peri_ck_26m_ck_p3", "infra_f26m_o0",
704 &infra0_cg_regs, 10),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]705 /* INFRA1 */
706 GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
707 "infra_66m_mck", 0),
708 GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
709 "infra_66m_mck", 1),
710 GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
711 "infra_pwm_sel", 2),
712 GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
713 "infra_pwm_ck1_sel", 3),
714 GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
715 "infra_pwm_ck2_sel", 4),
716 GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
717 "infra_pwm_ck3_sel", 5),
718 GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
719 "infra_pwm_ck4_sel", 6),
720 GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
721 "infra_pwm_ck5_sel", 7),
722 GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
723 "infra_pwm_ck6_sel", 8),
724 GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
725 "infra_pwm_ck7_sel", 9),
726 GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
727 "infra_pwm_ck8_sel", 10),
728 GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
729 "infra_133m_mck", 12),
730 GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
731 "infra_66m_phck", 13),
732 GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", "infra_ck_f26m", 14),
733 GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", "infra_faud_l_o", 15),
734 GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", "infra_faud_aud_o",
735 16),
736 GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", "infra_faud_eg2_o",
737 18),
738 GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "infra_ck_f26m",
739 19),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]740 GATE_CRITICAL(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
741 "infra_133m_mck", &infra1_cg_regs, 20),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]742 GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
743 "infra_66m_mck", 21),
744 GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
745 "infra_66m_mck", 29),
746 GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
747 "infra_ck_f26m", 30),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]748 /* INFRA2 */
749 GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
750 "infra_ck_f26m", 0),
751 GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", "infra_i2c_o", 1),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]752 GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
753 "infra_mux_uart0_sel", 3),
754 GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
755 "infra_mux_uart1_sel", 4),
756 GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
757 "infra_mux_uart2_sel", 5),
758 GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", "infra_nfi_o", 9),
759 GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", "infra_spinfi_o", 10),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]760 GATE_CRITICAL(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
761 "infra_66m_mck", &infra2_cg_regs, 11),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]762 GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
763 "infra_mux_spi0_sel", 12),
764 GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
765 "infra_mux_spi1_sel", 13),
766 GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
767 "infra_mux_spi2_sel", 14),
768 GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
769 "infra_66m_mck", 15),
770 GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
771 "infra_66m_mck", 16),
772 GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
773 "infra_66m_mck", 17),
774 GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
775 "infra_66m_mck", 18),
developera079b6a2023-02-22 14:49:06 +0800[diff] [blame]776 GATE_CRITICAL(CK_INFRA_RTC, "infra_f_frtc", "infra_lb_mux_frtc",
777 &infra2_cg_regs, 19),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]778 GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
779 "infra_f26m_o1", 20),
780 GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
781 21),
782 GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", "infra_fmsdc400_o",
783 22),
784 GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
785 "infra_fmsdc2_hck_occ", 23),
786 GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
787 "infra_peri_133m", 24),
788 GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
789 "infra_66m_phck", 25),
790 GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
791 "infra_133m_mck", 26),
792 GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "infra_nfi_o", 27),
793 GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
794 "infra_133m_mck", 29),
795 GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
796 "infra_66m_phck", 31),
797 /* INFRA3 */
798 GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
799 "infra_133m_phck", 0),
800 GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
801 "infra_133m_phck", 1),
802 GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "infra_66m_phck",
803 2),
804 GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
805 "infra_66m_phck", 3),
806 GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", "infra_usb_sys_o", 4),
807 GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
808 "infra_usb_sys_o_p1", 5),
809 GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", "infra_usb_o", 6),
810 GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "infra_usb_o_p1", 7),
developeref309762023-01-11 15:53:46 +0800[diff] [blame]811 GATE_CRITICAL(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
812 "infra_usb_frmcnt_o", &infra3_cg_regs, 8),
813 GATE_CRITICAL(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
814 "infra_usb_frmcnt_o_p1", &infra3_cg_regs, 9),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]815 GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", "infra_usb_pipe_o",
816 10),
817 GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
818 "infra_usb_pipe_o_p1", 11),
819 GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", "infra_usb_utmi_o",
820 12),
821 GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
822 "infra_usb_utmi_o_p1", 13),
823 GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", "infra_usb_xhci_o",
824 14),
825 GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
826 "infra_usb_xhci_o_p1", 15),
827 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
828 "infra_pcie_gfmux_tl_o_p0_sel", 20),
829 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
830 "infra_pcie_gfmux_tl_o_p1_sel", 21),
831 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
832 "infra_pcie_gfmux_tl_o_p2_sel", 22),
833 GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
834 "infra_pcie_gfmux_tl_o_p3_sel", 23),
835 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
836 "infra_pcie_pipe_ck_occ_p0", 24),
837 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
838 "infra_pcie_pipe_ck_occ_p1", 25),
839 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
840 "infra_pcie_pipe_ck_occ_p2", 26),
841 GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
842 "infra_pcie_pipe_ck_occ_p3", 27),
843 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
844 "infra_133m_phck", 28),
845 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
846 "infra_133m_phck", 29),
847 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
848 "infra_133m_phck", 30),
849 GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
850 "infra_133m_phck", 31),
851};
852
853static const struct mtk_gate_regs sgmii0_cg_regs = {
854 .set_ofs = 0xE4,
855 .clr_ofs = 0xE4,
856 .sta_ofs = 0xE4,
857};
858
859#define GATE_SGMII0(_id, _name, _parent, _shift) \
860 { \
861 .id = _id, .name = _name, .parent_name = _parent, \
862 .regs = &sgmii0_cg_regs, .shift = _shift, \
863 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
864 }
865
866static const struct mtk_gate sgmii0_clks[] __initconst = {
867 GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", "clkxtal", 2),
868 GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", "clkxtal", 3),
869};
870
871static const struct mtk_gate_regs sgmii1_cg_regs = {
872 .set_ofs = 0xE4,
873 .clr_ofs = 0xE4,
874 .sta_ofs = 0xE4,
875};
876
877#define GATE_SGMII1(_id, _name, _parent, _shift) \
878 { \
879 .id = _id, .name = _name, .parent_name = _parent, \
880 .regs = &sgmii1_cg_regs, .shift = _shift, \
881 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
882 }
883
884static const struct mtk_gate sgmii1_clks[] __initconst = {
885 GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", "clkxtal", 2),
886 GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", "clkxtal", 3),
887};
888
889static const struct mtk_gate_regs ethdma_cg_regs = {
890 .set_ofs = 0x30,
891 .clr_ofs = 0x30,
892 .sta_ofs = 0x30,
893};
894
895#define GATE_ETHDMA(_id, _name, _parent, _shift) \
896 { \
897 .id = _id, .name = _name, .parent_name = _parent, \
898 .regs = &ethdma_cg_regs, .shift = _shift, \
899 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
900 }
901
902static const struct mtk_gate ethdma_clks[] __initconst = {
903 GATE_ETHDMA(CK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "clkxtal", 0),
904 GATE_ETHDMA(CK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "clkxtal", 1),
905 GATE_ETHDMA(CK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "clkxtal", 2),
906 GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x", 6),
907 GATE_ETHDMA(CK_ETHDMA_GP2_EN, "ethdma_gp2_en", "clkxtal", 7),
908 GATE_ETHDMA(CK_ETHDMA_GP1_EN, "ethdma_gp1_en", "clkxtal", 8),
909 GATE_ETHDMA(CK_ETHDMA_GP3_EN, "ethdma_gp3_en", "clkxtal", 10),
910 GATE_ETHDMA(CK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw", 16),
911 GATE_ETHDMA(CK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197", 29),
912};
913
914static const struct mtk_gate_regs ethwarp_cg_regs = {
915 .set_ofs = 0x14,
916 .clr_ofs = 0x14,
917 .sta_ofs = 0x14,
918};
919
920#define GATE_ETHWARP(_id, _name, _parent, _shift) \
921 { \
922 .id = _id, .name = _name, .parent_name = _parent, \
923 .regs = &ethwarp_cg_regs, .shift = _shift, \
924 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
925 }
926
927static const struct mtk_gate ethwarp_clks[] __initconst = {
928 GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
929 "netsys_wed_mcu", 13),
930 GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
931 "netsys_wed_mcu", 14),
932 GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
933 "netsys_wed_mcu", 15),
934};
935
936#define MT7988_PLL_FMAX (2500UL * MHZ)
937#define MT7988_PCW_CHG_SHIFT 2
938
939#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
940 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
941 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _div_table, \
942 _parent_name) \
943 { \
944 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
945 .en_mask = _en_mask, .flags = _flags, \
946 .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
947 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
948 .tuner_reg = _tuner_reg, .tuner_en_reg = _tuner_en_reg, \
949 .tuner_en_bit = _tuner_en_bit, .pcw_reg = _pcw_reg, \
950 .pcw_shift = _pcw_shift, .pcw_chg_reg = _pcw_chg_reg, \
951 .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
952 .div_table = _div_table, .parent_name = _parent_name, \
953 }
954
955#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
956 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
957 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _parent_name) \
958 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
959 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
960 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL, \
961 _parent_name)
962
963static const struct mtk_pll_data plls[] = {
964 PLL(CK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0,
965 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104, "clkxtal"),
966 PLL(CK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
967 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114, "clkxtal"),
968 PLL(CK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR,
969 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124, "clkxtal"),
970 PLL(CK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
971 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134, "clkxtal"),
972 PLL(CK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
973 HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144,
974 "clkxtal"),
975 PLL(CK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
developeref309762023-01-11 15:53:46 +0800[diff] [blame]976 HAVE_RST_BAR | PLL_AO, 23, 32, 0x0154, 4, 0, 0, 0, 0x0158,
977 0, 0x0154, "clkxtal"),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]978 PLL(CK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0,
979 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164, "clkxtal"),
980 PLL(CK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
981 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174, "clkxtal"),
982 PLL(CK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, HAVE_RST_BAR,
983 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204, "clkxtal"),
984 PLL(CK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
985 HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214,
986 "clkxtal"),
987 PLL(CK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
988 HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304,
989 "clkxtal"),
990 PLL(CK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32,
991 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314, "clkxtal"),
992};
993
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]994static struct clk_onecell_data *mt7988_infra_clk_data __initdata;
995static struct clk_onecell_data *mt7988_infra_ao_clk_data __initdata;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]996static struct clk_onecell_data *mt7988_top_clk_data __initdata;
997static struct clk_onecell_data *mt7988_pll_clk_data __initdata;
998
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]999static void __init mtk_infracfg_init(struct device_node *node)
1000{
1001 int r;
1002
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1003 mt7988_infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1004
1005 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs),
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1006 mt7988_infra_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1007
1008 r = of_clk_add_provider(node, of_clk_src_onecell_get,
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1009 mt7988_infra_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1010
1011 if (r)
1012 pr_err("%s(): could not register clock provider: %d\n",
1013 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1014}
1015CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt7988-infracfg", mtk_infracfg_init);
1016
1017static void __init mtk_topckgen_init(struct device_node *node)
1018{
1019 int r;
1020 void __iomem *base;
1021
1022 base = of_iomap(node, 0);
1023 if (!base) {
1024 pr_err("%s(): ioremap failed\n", __func__);
1025 return;
1026 }
1027
1028 mt7988_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1029
1030 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
1031 mt7988_top_clk_data);
1032 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
1033 &mt7988_clk_lock, mt7988_top_clk_data);
developer4323f7e2022-10-13 11:09:46 +0800[diff] [blame]1034 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1035 base, &mt7988_clk_lock, mt7988_top_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1036 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1037 mt7988_top_clk_data);
1038
1039 if (r)
1040 pr_err("%s(): could not register clock provider: %d\n",
1041 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1042}
1043CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7988-topckgen", mtk_topckgen_init);
1044
1045static void __init mtk_infracfg_ao_init(struct device_node *node)
1046{
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1047 int r;
1048 void __iomem *base;
1049
1050 base = of_iomap(node, 0);
1051 if (!base) {
1052 pr_err("%s(): ioremap failed\n", __func__);
1053 return;
1054 }
1055
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1056 mt7988_infra_ao_clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1057
1058 mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1059 &mt7988_clk_lock, mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1060 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1061 mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1062
developer1a5527e2022-11-01 10:52:44 +0800[diff] [blame]1063 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1064 mt7988_infra_ao_clk_data);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1065
1066 if (r)
1067 pr_err("%s(): could not register clock provider: %d\n",
1068 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1069}
1070CLK_OF_DECLARE(mtk_infracfg_ao, "mediatek,mt7988-infracfg_ao",
1071 mtk_infracfg_ao_init);
1072
1073static void __init mtk_apmixedsys_init(struct device_node *node)
1074{
1075 int r;
1076
1077 mt7988_pll_clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1078
1079 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
1080 mt7988_pll_clk_data);
1081
1082 r = of_clk_add_provider(node, of_clk_src_onecell_get,
1083 mt7988_pll_clk_data);
1084
1085 if (r)
1086 pr_err("%s(): could not register clock provider: %d\n",
1087 __func__, r);
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1088}
1089CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7988-apmixedsys",
1090 mtk_apmixedsys_init);
1091
1092static void __init mtk_mcusys_init(struct device_node *node)
1093{
1094 struct clk_onecell_data *clk_data;
1095 int r;
1096 void __iomem *base;
1097
1098 base = of_iomap(node, 0);
1099 if (!base) {
1100 pr_err("%s(): ioremap failed\n", __func__);
1101 return;
1102 }
1103
1104 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1105 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1106 &mt7988_clk_lock, clk_data);
1107
1108 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1109
1110 if (r)
1111 pr_err("%s(): could not register clock provider: %d\n",
1112 __func__, r);
1113}
1114CLK_OF_DECLARE(mtk_mcusys, "mediatek,mt7988-mcusys", mtk_mcusys_init);
1115
1116static void __init mtk_sgmiisys_0_init(struct device_node *node)
1117{
1118 struct clk_onecell_data *clk_data;
1119 int r;
1120
1121 clk_data = mtk_alloc_clk_data(CLK_SGMII0_NR_CLK);
1122
1123 mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
1124 clk_data);
1125
1126 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1127
1128 if (r)
1129 pr_err("%s(): could not register clock provider: %d\n",
1130 __func__, r);
1131}
1132CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7988-sgmiisys_0",
1133 mtk_sgmiisys_0_init);
1134
1135static void __init mtk_sgmiisys_1_init(struct device_node *node)
1136{
1137 struct clk_onecell_data *clk_data;
1138 int r;
1139
1140 clk_data = mtk_alloc_clk_data(CLK_SGMII1_NR_CLK);
1141
1142 mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
1143 clk_data);
1144
1145 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1146
1147 if (r)
1148 pr_err("%s(): could not register clock provider: %d\n",
1149 __func__, r);
1150}
1151CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7988-sgmiisys_1",
1152 mtk_sgmiisys_1_init);
1153
1154static void __init mtk_ethdma_init(struct device_node *node)
1155{
1156 struct clk_onecell_data *clk_data;
1157 int r;
1158
1159 clk_data = mtk_alloc_clk_data(CLK_ETHDMA_NR_CLK);
1160
1161 mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
1162 clk_data);
1163
1164 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1165
1166 if (r)
1167 pr_err("%s(): could not register clock provider: %d\n",
1168 __func__, r);
1169}
1170CLK_OF_DECLARE(mtk_ethdma, "mediatek,mt7988-ethsys", mtk_ethdma_init);
1171
1172static void __init mtk_ethwarp_init(struct device_node *node)
1173{
1174 struct clk_onecell_data *clk_data;
1175 int r;
1176
1177 clk_data = mtk_alloc_clk_data(CLK_ETHWARP_NR_CLK);
1178
1179 mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
1180 clk_data);
1181
1182 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1183
1184 if (r)
1185 pr_err("%s(): could not register clock provider: %d\n",
1186 __func__, r);
1187}
1188CLK_OF_DECLARE(mtk_ethwarp, "mediatek,mt7988-ethwarp", mtk_ethwarp_init);