developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // Copyright (c) 2018-2019 MediaTek Inc. |
| 3 | |
| 4 | /* A library for MediaTek SGMII circuit |
| 5 | * |
| 6 | * Author: Sean Wang <sean.wang@mediatek.com> |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/mfd/syscon.h> |
| 11 | #include <linux/of.h> |
| 12 | #include <linux/regmap.h> |
| 13 | |
| 14 | #include "mtk_eth_soc.h" |
| 15 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 16 | int mtk_sgmii_init(struct mtk_xgmii *ss, struct device_node *r, u32 ana_rgc3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 17 | { |
| 18 | struct device_node *np; |
| 19 | int i; |
| 20 | |
| 21 | ss->ana_rgc3 = ana_rgc3; |
| 22 | |
| 23 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 24 | np = of_parse_phandle(r, "mediatek,sgmiisys", i); |
| 25 | if (!np) |
| 26 | break; |
| 27 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 28 | ss->regmap_sgmii[i] = syscon_node_to_regmap(np); |
| 29 | if (IS_ERR(ss->regmap_sgmii[i])) |
| 30 | return PTR_ERR(ss->regmap_sgmii[i]); |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 31 | |
| 32 | ss->flags[i] &= ~(MTK_SGMII_PN_SWAP); |
| 33 | if (of_property_read_bool(np, "pn_swap")) |
| 34 | ss->flags[i] |= MTK_SGMII_PN_SWAP; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame^] | 40 | void mtk_sgmii_reset(struct mtk_xgmii *ss, int mac_id) |
| 41 | { |
| 42 | struct mtk_eth *eth = ss->eth; |
| 43 | u32 id = mtk_mac2xgmii_id(eth, mac_id); |
| 44 | u32 val = 0; |
| 45 | |
| 46 | if (id >= MTK_MAX_DEVS || !eth->toprgu) |
| 47 | return; |
| 48 | |
| 49 | switch (mac_id) { |
| 50 | case MTK_GMAC2_ID: |
| 51 | /* Enable software reset */ |
| 52 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
| 53 | val |= SWSYSRST_XFI_PEXPT1_GRST | |
| 54 | SWSYSRST_SGMII1_GRST; |
| 55 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 56 | |
| 57 | /* Assert SGMII reset */ |
| 58 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 59 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | |
| 60 | SWSYSRST_XFI_PEXPT1_GRST | |
| 61 | SWSYSRST_SGMII1_GRST; |
| 62 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 63 | |
| 64 | udelay(100); |
| 65 | |
| 66 | /* De-assert SGMII reset */ |
| 67 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 68 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); |
| 69 | val &= ~(SWSYSRST_XFI_PEXPT1_GRST | |
| 70 | SWSYSRST_SGMII1_GRST); |
| 71 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 72 | |
| 73 | /* Disable software reset */ |
| 74 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
| 75 | val &= ~(SWSYSRST_XFI_PEXPT1_GRST | |
| 76 | SWSYSRST_SGMII1_GRST); |
| 77 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 78 | break; |
| 79 | case MTK_GMAC3_ID: |
| 80 | /* Enable Software reset */ |
| 81 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
| 82 | val |= SWSYSRST_XFI_PEXPT0_GRST | |
| 83 | SWSYSRST_SGMII0_GRST; |
| 84 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 85 | |
| 86 | /* Assert SGMII reset */ |
| 87 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 88 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | |
| 89 | SWSYSRST_XFI_PEXPT0_GRST | |
| 90 | SWSYSRST_SGMII0_GRST; |
| 91 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 92 | |
| 93 | udelay(100); |
| 94 | |
| 95 | /* De-assert SGMII reset */ |
| 96 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 97 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); |
| 98 | val &= ~(SWSYSRST_XFI_PEXPT0_GRST | |
| 99 | SWSYSRST_SGMII0_GRST); |
| 100 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 101 | |
| 102 | /* Disable software reset */ |
| 103 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
| 104 | val &= ~(SWSYSRST_XFI_PEXPT0_GRST | |
| 105 | SWSYSRST_SGMII0_GRST); |
| 106 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 107 | break; |
| 108 | } |
| 109 | |
| 110 | mdelay(1); |
| 111 | } |
| 112 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 113 | void mtk_sgmii_setup_phya_gen1(struct mtk_xgmii *ss, int mac_id) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 114 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 115 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
| 116 | |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 117 | if (id >= MTK_MAX_DEVS || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 118 | !ss->regmap_sgmii[id] || !ss->regmap_pextp[id]) |
| 119 | return; |
| 120 | |
| 121 | regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00D9071C); |
| 122 | regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA); |
| 123 | regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020207); |
| 124 | regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E05050F); |
| 125 | regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00200032); |
| 126 | regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014BA); |
| 127 | regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B); |
| 128 | regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF); |
| 129 | regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA); |
| 130 | regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F); |
| 131 | regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68); |
| 132 | regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166); |
| 133 | regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000EAF); |
| 134 | regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080E0D); |
| 135 | regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030B09); |
| 136 | regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000); |
| 137 | regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000); |
| 138 | regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0606); |
| 139 | regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C); |
| 140 | regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000); |
| 141 | regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x00FA32FA); |
| 142 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F21); |
| 143 | regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00); |
| 144 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800); |
| 145 | ndelay(1020); |
| 146 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020); |
| 147 | regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01); |
| 148 | regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884); |
| 149 | regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002); |
| 150 | regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00011110); |
| 151 | regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000); |
| 152 | regmap_update_bits(ss->regmap_pextp[id], 0x3064, GENMASK(31, 0), 0x0000C000); |
| 153 | regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000); |
| 154 | regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA); |
| 155 | regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x20200F00); |
| 156 | regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00050000); |
| 157 | regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000007); |
| 158 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800); |
| 159 | udelay(150); |
| 160 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111); |
| 161 | ndelay(1020); |
| 162 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101); |
| 163 | udelay(15); |
| 164 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C111); |
| 165 | ndelay(1020); |
| 166 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C101); |
| 167 | udelay(100); |
| 168 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030); |
| 169 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F01); |
| 170 | regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000); |
| 171 | udelay(400); |
| 172 | } |
| 173 | |
| 174 | void mtk_sgmii_setup_phya_gen2(struct mtk_xgmii *ss, int mac_id) |
| 175 | { |
| 176 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
| 177 | |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 178 | if (id >= MTK_MAX_DEVS || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 179 | !ss->regmap_sgmii[id] || !ss->regmap_pextp[id]) |
| 180 | return; |
| 181 | |
| 182 | regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00D9071C); |
| 183 | regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA); |
| 184 | regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707); |
| 185 | regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F); |
| 186 | regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032); |
| 187 | regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA); |
| 188 | regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B); |
| 189 | regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF); |
| 190 | regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA); |
| 191 | regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F); |
| 192 | regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68); |
| 193 | regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166); |
| 194 | regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF); |
| 195 | regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D); |
| 196 | regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909); |
| 197 | regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000); |
| 198 | regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000); |
| 199 | regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06); |
| 200 | regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C); |
| 201 | regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000); |
| 202 | regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x009C329C); |
| 203 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F21); |
| 204 | regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00); |
| 205 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800); |
| 206 | ndelay(1020); |
| 207 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020); |
| 208 | regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01); |
| 209 | regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884); |
| 210 | regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002); |
| 211 | regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00011110); |
| 212 | regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000); |
| 213 | regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000); |
| 214 | regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA); |
| 215 | regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x22000F00); |
| 216 | regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00050000); |
| 217 | regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000005); |
| 218 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800); |
| 219 | udelay(150); |
| 220 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111); |
| 221 | ndelay(1020); |
| 222 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101); |
| 223 | udelay(15); |
| 224 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C111); |
| 225 | ndelay(1020); |
| 226 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C101); |
| 227 | udelay(100); |
| 228 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030); |
| 229 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F01); |
| 230 | regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000); |
| 231 | udelay(400); |
| 232 | } |
| 233 | |
| 234 | int mtk_sgmii_setup_mode_an(struct mtk_xgmii *ss, unsigned int mac_id) |
| 235 | { |
| 236 | struct mtk_eth *eth = ss->eth; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 237 | unsigned int val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 238 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 239 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 240 | if (!ss->regmap_sgmii[id]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 241 | return -EINVAL; |
| 242 | |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame^] | 243 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 244 | mtk_xfi_pll_enable(ss); |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame^] | 245 | mtk_sgmii_reset(ss, mac_id); |
| 246 | } |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 247 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 248 | /* Assert PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 249 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 250 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 251 | /* Reset SGMII PCS state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 252 | regmap_write(ss->regmap_sgmii[id], SGMII_RESERVED_0, SGMII_SW_RESET); |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 253 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 254 | regmap_read(ss->regmap_sgmii[id], ss->ana_rgc3, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 255 | val &= ~RG_PHY_SPEED_3_125G; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 256 | regmap_write(ss->regmap_sgmii[id], ss->ana_rgc3, val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 257 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 258 | /* Setup the link timer and QPHY power up inside SGMIISYS */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 259 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_LINK_TIMER, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 260 | SGMII_LINK_TIMER_DEFAULT); |
| 261 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 262 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 263 | val |= SGMII_REMOTE_FAULT_DIS; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 264 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 265 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 266 | /* SGMII AN mode setting */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 267 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 268 | val &= ~SGMII_IF_MODE_MASK; |
| 269 | val |= SGMII_SPEED_DUPLEX_AN; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 270 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 271 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 272 | /* Enable SGMII AN */ |
| 273 | regmap_read(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 274 | val |= SGMII_AN_ENABLE; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 275 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 276 | |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 277 | if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 278 | regmap_update_bits(ss->regmap_sgmii[id], SGMSYS_QPHY_WRAP_CTRL, |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 279 | SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX); |
| 280 | |
developer | 3d014da | 2022-05-11 16:29:59 +0800 | [diff] [blame] | 281 | /* Release PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 282 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 283 | |
| 284 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 285 | mtk_sgmii_setup_phya_gen1(ss, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 290 | int mtk_sgmii_setup_mode_force(struct mtk_xgmii *ss, unsigned int mac_id, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 291 | const struct phylink_link_state *state) |
| 292 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 293 | struct mtk_eth *eth = ss->eth; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 294 | unsigned int val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 295 | u32 id = mtk_mac2xgmii_id(eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 296 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 297 | if (!ss->regmap_sgmii[id]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 298 | return -EINVAL; |
| 299 | |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame^] | 300 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 301 | mtk_xfi_pll_enable(ss); |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame^] | 302 | mtk_sgmii_reset(ss, mac_id); |
| 303 | } |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 304 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 305 | /* Assert PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 306 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 307 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 308 | /* Reset SGMII PCS state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 309 | regmap_write(ss->regmap_sgmii[id], SGMII_RESERVED_0, SGMII_SW_RESET); |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 310 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 311 | regmap_read(ss->regmap_sgmii[id], ss->ana_rgc3, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 312 | val &= ~RG_PHY_SPEED_MASK; |
| 313 | if (state->interface == PHY_INTERFACE_MODE_2500BASEX) |
| 314 | val |= RG_PHY_SPEED_3_125G; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 315 | regmap_write(ss->regmap_sgmii[id], ss->ana_rgc3, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 316 | |
| 317 | /* Disable SGMII AN */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 318 | regmap_read(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 319 | val &= ~SGMII_AN_ENABLE; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 320 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 321 | |
| 322 | /* SGMII force mode setting */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 323 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 324 | val &= ~SGMII_IF_MODE_MASK; |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 325 | val &= ~SGMII_REMOTE_FAULT_DIS; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 326 | |
| 327 | switch (state->speed) { |
| 328 | case SPEED_10: |
| 329 | val |= SGMII_SPEED_10; |
| 330 | break; |
| 331 | case SPEED_100: |
| 332 | val |= SGMII_SPEED_100; |
| 333 | break; |
| 334 | case SPEED_2500: |
| 335 | case SPEED_1000: |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 336 | default: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 337 | val |= SGMII_SPEED_1000; |
| 338 | break; |
| 339 | }; |
| 340 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 341 | /* SGMII 1G and 2.5G force mode can only work in full duplex |
| 342 | * mode, no matter SGMII_FORCE_HALF_DUPLEX is set or not. |
| 343 | */ |
| 344 | if (state->duplex != DUPLEX_FULL) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 345 | val |= SGMII_DUPLEX_FULL; |
| 346 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 347 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 348 | |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 349 | if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 350 | regmap_update_bits(ss->regmap_sgmii[id], SGMSYS_QPHY_WRAP_CTRL, |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 351 | SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX); |
developer | 3d014da | 2022-05-11 16:29:59 +0800 | [diff] [blame] | 352 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 353 | /* Release PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 354 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 355 | |
| 356 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 357 | mtk_sgmii_setup_phya_gen2(ss, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 358 | |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) |
| 363 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 364 | struct mtk_xgmii *ss = eth->xgmii; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 365 | unsigned int val = 0, sid = mtk_mac2xgmii_id(eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 366 | |
| 367 | /* Decide how GMAC and SGMIISYS be mapped */ |
| 368 | sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 369 | 0 : sid; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 370 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 371 | if (!ss->regmap_sgmii[sid]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 372 | return; |
| 373 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 374 | regmap_read(ss->regmap_sgmii[sid], SGMSYS_PCS_CONTROL_1, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 375 | val |= SGMII_AN_RESTART; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 376 | regmap_write(ss->regmap_sgmii[sid], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 377 | } |