developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // Copyright (c) 2018-2019 MediaTek Inc. |
| 3 | |
| 4 | /* A library for MediaTek SGMII circuit |
| 5 | * |
| 6 | * Author: Sean Wang <sean.wang@mediatek.com> |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/mfd/syscon.h> |
| 11 | #include <linux/of.h> |
| 12 | #include <linux/regmap.h> |
| 13 | |
| 14 | #include "mtk_eth_soc.h" |
| 15 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 16 | int mtk_sgmii_init(struct mtk_xgmii *ss, struct device_node *r, u32 ana_rgc3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 17 | { |
| 18 | struct device_node *np; |
| 19 | int i; |
| 20 | |
| 21 | ss->ana_rgc3 = ana_rgc3; |
| 22 | |
| 23 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 24 | np = of_parse_phandle(r, "mediatek,sgmiisys", i); |
| 25 | if (!np) |
| 26 | break; |
| 27 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 28 | ss->regmap_sgmii[i] = syscon_node_to_regmap(np); |
| 29 | if (IS_ERR(ss->regmap_sgmii[i])) |
| 30 | return PTR_ERR(ss->regmap_sgmii[i]); |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 31 | |
| 32 | ss->flags[i] &= ~(MTK_SGMII_PN_SWAP); |
| 33 | if (of_property_read_bool(np, "pn_swap")) |
| 34 | ss->flags[i] |= MTK_SGMII_PN_SWAP; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 40 | void mtk_sgmii_setup_phya_gen1(struct mtk_xgmii *ss, int mac_id) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 41 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 42 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
| 43 | |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 44 | if (id >= MTK_MAX_DEVS || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 45 | !ss->regmap_sgmii[id] || !ss->regmap_pextp[id]) |
| 46 | return; |
| 47 | |
| 48 | regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00D9071C); |
| 49 | regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA); |
| 50 | regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020207); |
| 51 | regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E05050F); |
| 52 | regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00200032); |
| 53 | regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014BA); |
| 54 | regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B); |
| 55 | regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF); |
| 56 | regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA); |
| 57 | regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F); |
| 58 | regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68); |
| 59 | regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166); |
| 60 | regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000EAF); |
| 61 | regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080E0D); |
| 62 | regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030B09); |
| 63 | regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000); |
| 64 | regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000); |
| 65 | regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0606); |
| 66 | regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C); |
| 67 | regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000); |
| 68 | regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x00FA32FA); |
| 69 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F21); |
| 70 | regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00); |
| 71 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800); |
| 72 | ndelay(1020); |
| 73 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020); |
| 74 | regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01); |
| 75 | regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884); |
| 76 | regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002); |
| 77 | regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00011110); |
| 78 | regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000); |
| 79 | regmap_update_bits(ss->regmap_pextp[id], 0x3064, GENMASK(31, 0), 0x0000C000); |
| 80 | regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000); |
| 81 | regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA); |
| 82 | regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x20200F00); |
| 83 | regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00050000); |
| 84 | regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000007); |
| 85 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800); |
| 86 | udelay(150); |
| 87 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111); |
| 88 | ndelay(1020); |
| 89 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101); |
| 90 | udelay(15); |
| 91 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C111); |
| 92 | ndelay(1020); |
| 93 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C101); |
| 94 | udelay(100); |
| 95 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030); |
| 96 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F01); |
| 97 | regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000); |
| 98 | udelay(400); |
| 99 | } |
| 100 | |
| 101 | void mtk_sgmii_setup_phya_gen2(struct mtk_xgmii *ss, int mac_id) |
| 102 | { |
| 103 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
| 104 | |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 105 | if (id >= MTK_MAX_DEVS || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 106 | !ss->regmap_sgmii[id] || !ss->regmap_pextp[id]) |
| 107 | return; |
| 108 | |
| 109 | regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00D9071C); |
| 110 | regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA); |
| 111 | regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707); |
| 112 | regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F); |
| 113 | regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032); |
| 114 | regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA); |
| 115 | regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B); |
| 116 | regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF); |
| 117 | regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA); |
| 118 | regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F); |
| 119 | regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68); |
| 120 | regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166); |
| 121 | regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF); |
| 122 | regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D); |
| 123 | regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909); |
| 124 | regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000); |
| 125 | regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000); |
| 126 | regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06); |
| 127 | regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C); |
| 128 | regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000); |
| 129 | regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x009C329C); |
| 130 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F21); |
| 131 | regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00); |
| 132 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800); |
| 133 | ndelay(1020); |
| 134 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020); |
| 135 | regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01); |
| 136 | regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884); |
| 137 | regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002); |
| 138 | regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00011110); |
| 139 | regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000); |
| 140 | regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000); |
| 141 | regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA); |
| 142 | regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x22000F00); |
| 143 | regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00050000); |
| 144 | regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000005); |
| 145 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800); |
| 146 | udelay(150); |
| 147 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111); |
| 148 | ndelay(1020); |
| 149 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101); |
| 150 | udelay(15); |
| 151 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C111); |
| 152 | ndelay(1020); |
| 153 | regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0201C101); |
| 154 | udelay(100); |
| 155 | regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030); |
| 156 | regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F01); |
| 157 | regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000); |
| 158 | udelay(400); |
| 159 | } |
| 160 | |
| 161 | int mtk_sgmii_setup_mode_an(struct mtk_xgmii *ss, unsigned int mac_id) |
| 162 | { |
| 163 | struct mtk_eth *eth = ss->eth; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 164 | unsigned int val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 165 | u32 id = mtk_mac2xgmii_id(ss->eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 166 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 167 | if (!ss->regmap_sgmii[id]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 168 | return -EINVAL; |
| 169 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 170 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 171 | mtk_xfi_pll_enable(ss); |
| 172 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 173 | /* Assert PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 174 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 175 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 176 | /* Reset SGMII PCS state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 177 | regmap_write(ss->regmap_sgmii[id], SGMII_RESERVED_0, SGMII_SW_RESET); |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 178 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 179 | regmap_read(ss->regmap_sgmii[id], ss->ana_rgc3, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 180 | val &= ~RG_PHY_SPEED_3_125G; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 181 | regmap_write(ss->regmap_sgmii[id], ss->ana_rgc3, val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 182 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 183 | /* Setup the link timer and QPHY power up inside SGMIISYS */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 184 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_LINK_TIMER, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 185 | SGMII_LINK_TIMER_DEFAULT); |
| 186 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 187 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 188 | val |= SGMII_REMOTE_FAULT_DIS; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 189 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 190 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 191 | /* SGMII AN mode setting */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 192 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 193 | val &= ~SGMII_IF_MODE_MASK; |
| 194 | val |= SGMII_SPEED_DUPLEX_AN; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 195 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 196 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 197 | /* Enable SGMII AN */ |
| 198 | regmap_read(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, &val); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 199 | val |= SGMII_AN_ENABLE; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 200 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 201 | |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 202 | if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 203 | regmap_update_bits(ss->regmap_sgmii[id], SGMSYS_QPHY_WRAP_CTRL, |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 204 | SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX); |
| 205 | |
developer | 3d014da | 2022-05-11 16:29:59 +0800 | [diff] [blame] | 206 | /* Release PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 207 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 208 | |
| 209 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 210 | mtk_sgmii_setup_phya_gen1(ss, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 211 | |
| 212 | return 0; |
| 213 | } |
| 214 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 215 | int mtk_sgmii_setup_mode_force(struct mtk_xgmii *ss, unsigned int mac_id, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 216 | const struct phylink_link_state *state) |
| 217 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 218 | struct mtk_eth *eth = ss->eth; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 219 | unsigned int val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 220 | u32 id = mtk_mac2xgmii_id(eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 221 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 222 | if (!ss->regmap_sgmii[id]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 223 | return -EINVAL; |
| 224 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 225 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 226 | mtk_xfi_pll_enable(ss); |
| 227 | |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 228 | /* Assert PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 229 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 230 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 231 | /* Reset SGMII PCS state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 232 | regmap_write(ss->regmap_sgmii[id], SGMII_RESERVED_0, SGMII_SW_RESET); |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 233 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 234 | regmap_read(ss->regmap_sgmii[id], ss->ana_rgc3, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 235 | val &= ~RG_PHY_SPEED_MASK; |
| 236 | if (state->interface == PHY_INTERFACE_MODE_2500BASEX) |
| 237 | val |= RG_PHY_SPEED_3_125G; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 238 | regmap_write(ss->regmap_sgmii[id], ss->ana_rgc3, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 239 | |
| 240 | /* Disable SGMII AN */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 241 | regmap_read(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 242 | val &= ~SGMII_AN_ENABLE; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 243 | regmap_write(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 244 | |
| 245 | /* SGMII force mode setting */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 246 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 247 | val &= ~SGMII_IF_MODE_MASK; |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 248 | val &= ~SGMII_REMOTE_FAULT_DIS; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 249 | |
| 250 | switch (state->speed) { |
| 251 | case SPEED_10: |
| 252 | val |= SGMII_SPEED_10; |
| 253 | break; |
| 254 | case SPEED_100: |
| 255 | val |= SGMII_SPEED_100; |
| 256 | break; |
| 257 | case SPEED_2500: |
| 258 | case SPEED_1000: |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 259 | default: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 260 | val |= SGMII_SPEED_1000; |
| 261 | break; |
| 262 | }; |
| 263 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 264 | /* SGMII 1G and 2.5G force mode can only work in full duplex |
| 265 | * mode, no matter SGMII_FORCE_HALF_DUPLEX is set or not. |
| 266 | */ |
| 267 | if (state->duplex != DUPLEX_FULL) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 268 | val |= SGMII_DUPLEX_FULL; |
| 269 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 270 | regmap_write(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 271 | |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 272 | if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 273 | regmap_update_bits(ss->regmap_sgmii[id], SGMSYS_QPHY_WRAP_CTRL, |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 274 | SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX); |
developer | 3d014da | 2022-05-11 16:29:59 +0800 | [diff] [blame] | 275 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 276 | /* Release PHYA power down state */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 277 | regmap_write(ss->regmap_sgmii[id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 278 | |
| 279 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 280 | mtk_sgmii_setup_phya_gen2(ss, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) |
| 286 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 287 | struct mtk_xgmii *ss = eth->xgmii; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame] | 288 | unsigned int val = 0, sid = mtk_mac2xgmii_id(eth, mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 289 | |
| 290 | /* Decide how GMAC and SGMIISYS be mapped */ |
| 291 | sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 292 | 0 : sid; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 293 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 294 | if (!ss->regmap_sgmii[sid]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 295 | return; |
| 296 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 297 | regmap_read(ss->regmap_sgmii[sid], SGMSYS_PCS_CONTROL_1, &val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 298 | val |= SGMII_AN_RESTART; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 299 | regmap_write(ss->regmap_sgmii[sid], SGMSYS_PCS_CONTROL_1, val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 300 | } |