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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / fd40db2c438e201a0ce1aad96c7250f7724cde41 / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / mediatek / mtk_sgmii.c
blob: 4db27dfc7ec1fa2691fba3b67d3bfd199e79190e [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018-2019 MediaTek Inc.
3
4/* A library for MediaTek SGMII circuit
5 *
6 * Author: Sean Wang <sean.wang@mediatek.com>
7 *
8 */
9
10#include <linux/mfd/syscon.h>
11#include <linux/of.h>
12#include <linux/regmap.h>
13
14#include "mtk_eth_soc.h"
15
16int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
17{
18 struct device_node *np;
19 int i;
20
21 ss->ana_rgc3 = ana_rgc3;
22
23 for (i = 0; i < MTK_MAX_DEVS; i++) {
24 np = of_parse_phandle(r, "mediatek,sgmiisys", i);
25 if (!np)
26 break;
27
28 ss->regmap[i] = syscon_node_to_regmap(np);
29 if (IS_ERR(ss->regmap[i]))
30 return PTR_ERR(ss->regmap[i]);
31 }
32
33 return 0;
34}
35
36int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
37{
38 unsigned int val;
39
40 if (!ss->regmap[id])
41 return -EINVAL;
42
43 /* Setup the link timer and QPHY power up inside SGMIISYS */
44 regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
45 SGMII_LINK_TIMER_DEFAULT);
46
47 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
48 val |= SGMII_REMOTE_FAULT_DIS;
49 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
50
51 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
52 val |= SGMII_AN_RESTART;
53 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
54
55 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
56 val &= ~SGMII_PHYA_PWD;
57 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
58
59 return 0;
60}
61
62int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
63 const struct phylink_link_state *state)
64{
65 unsigned int val;
66
67 if (!ss->regmap[id])
68 return -EINVAL;
69
70 regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
71 val &= ~RG_PHY_SPEED_MASK;
72 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
73 val |= RG_PHY_SPEED_3_125G;
74 regmap_write(ss->regmap[id], ss->ana_rgc3, val);
75
76 /* Disable SGMII AN */
77 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
78 val &= ~SGMII_AN_ENABLE;
79 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
80
81 /* SGMII force mode setting */
82 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
83 val &= ~SGMII_IF_MODE_MASK;
84
85 switch (state->speed) {
86 case SPEED_10:
87 val |= SGMII_SPEED_10;
88 break;
89 case SPEED_100:
90 val |= SGMII_SPEED_100;
91 break;
92 case SPEED_2500:
93 case SPEED_1000:
94 val |= SGMII_SPEED_1000;
95 break;
96 };
97
98 if (state->duplex == DUPLEX_FULL)
99 val |= SGMII_DUPLEX_FULL;
100
101 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
102
103 /* Release PHYA power down state */
104 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
105 val &= ~SGMII_PHYA_PWD;
106 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
107
108 return 0;
109}
110
111void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
112{
113 struct mtk_sgmii *ss = eth->sgmii;
114 unsigned int val, sid;
115
116 /* Decide how GMAC and SGMIISYS be mapped */
117 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
118 0 : mac_id;
119
120 if (!ss->regmap[sid])
121 return;
122
123 regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
124 val |= SGMII_AN_RESTART;
125 regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
126}