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git01.mediatek.com / filogic / uboot / d8e694269ee53c5c24e2df340138128c3f851f93 / drivers / ddr
  1. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  2. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · 7 years ago
  3. d3e6816 Revert "drivers/ddr/fsl: Dual-license DDR driver" by Tom Rini · 7 years ago
  4. 6d49eda drivers/ddr/fsl: Dual-license DDR driver by York Sun · 7 years ago
  5. 74588bb drivers/ddr/fsl: Cleanup unused variable by York Sun · 7 years ago
  6. 194c2f4 drivers/ddr/fsl: Modify binding registers to save time on data init by York Sun · 7 years ago
  7. bc2f32a drivers/ddr/fsl: Add calculation of register control words by York Sun · 7 years ago
  8. 6db4fdd drivers/ddr/fsl: Add 3DS RDIMM support by York Sun · 7 years ago
  9. 2a4859e drivers/ddr/fsl: Fix workaround for A009803 by York Sun · 7 years ago
  10. d9f7fa0 drivers/ddr/fsl: Fix DDR4 RDIMM support by York Sun · 7 years ago
  11. c00a369 Merge git://git.denx.de/u-boot-socfpga by Tom Rini · 7 years ago
  12. 60649bb Merge git://git.denx.de/u-boot-spi by Tom Rini · 7 years ago
  13. a4af914 ddr: altera: silence PHY calibration unless in debug mode by Goldschmidt Simon · 7 years ago
  14. 918de03 wait_bit: use wait_for_bit_le32 and remove wait_for_bit by Álvaro Fernández Rojas · 7 years ago
  15. 661bc24 ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs by Rajesh Bhagat · 7 years ago
  16. 5450f0c ddr: marvell: update ddr controller init and freq by Chris Packham · 7 years ago
  17. d5c581c ddr: marvell: update additional ODT setting by Chris Packham · 7 years ago
  18. 1324fab ddr: marvell: use correct TREFI value by Chris Packham · 7 years ago
  19. ae80614 ddr: marvell: only assert M_ODT[0] on write for a single CS by Chris Packham · 7 years ago
  20. b25faa2 armv8: ls1088a: Add NXP LS1088A SoC support by Ashish Kumar · 7 years ago
  21. 64b723f env: Rename getenv/_f() to env_get() by Simon Glass · 7 years ago
  22. 273d3f7 arm: mvebu: ddr3_debug: remove self assignments by xypron.glpk@gmx.de · 7 years ago
  23. 94e8daa arm: mvebu: remove self assignment by xypron.glpk@gmx.de · 7 years ago
  24. f8bf75f driver/ddr: Add support for setting timing in hws_topology_map by Marek Behún · 7 years ago
  25. 622b7b3 treewide: remove unneeded semicolons by Masahiro Yamada · 7 years ago
  26. f43278e driver: ddr: fsl: Fix compiling error for DDR2 by York Sun · 8 years ago
  27. 89e0a3a common: arm: freescale: layerscape: Move header files out of common.h by Simon Glass · 8 years ago
  28. 243182c common: freescale: Move arch-specific declarations by Simon Glass · 8 years ago
  29. cffa503 Merge git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · 8 years ago
  30. 5fecf83 ddr: fsl: incorrect logical constraint in populate_memctl_options by xypron.glpk@gmx.de · 8 years ago
  31. 7d2e8e4 drivers: ddr: fsl: fix unused-const-variable warnings by Thomas Schaefer · 8 years ago
  32. 03017c5 Merge branch 'master' of git://git.denx.de/u-boot-socfpga by Tom Rini · 8 years ago
  33. 016539e arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig by Ley Foon Tan · 8 years ago
  34. d35f338 board_f: Rename initdram() to dram_init() by Simon Glass · 8 years ago
  35. 39f90ba board_f: Drop return value from initdram() by Simon Glass · 8 years ago
  36. fe84507 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS by York Sun · 8 years ago
  37. dcd28c0 ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig by York Sun · 8 years ago
  38. be73553 powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig by York Sun · 8 years ago
  39. 1dc61ca arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig by York Sun · 8 years ago
  40. d297d39 fsl_ddr: Move DDR config options to driver Kconfig by York Sun · 8 years ago
  41. 15875a5 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum by Shengzhou Liu · 8 years ago
  42. 7566ac1 fsl/ddr: Fix compiling warning by Shengzhou Liu · 8 years ago
  43. 32be34d powerpc: MPC8555: Remove macro CONFIG_MPC8555 by York Sun · 8 years ago
  44. bf820c0 powerpc: mpc8541: Remove macro CONFIG_MPC8541 by York Sun · 8 years ago
  45. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · 8 years ago
  46. c5b1e5d Various, accumulated typos collected from around the tree. by Robert P. J. Day · 8 years ago
  47. 71c10a4 Merge git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · 8 years ago
  48. c1e979b driver: ddr: fsl_mmdc: Pass board parameters through data structure by York Sun · 8 years ago
  49. 30fe357 drivers: squash lines for immediate return by Masahiro Yamada · 8 years ago
  50. 3350e37 ddr: fsl: fix a compile issue by Shaohui Xie · 8 years ago
  51. cb7fb12 driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a by Shengzhou Liu · 8 years ago
  52. 36af3d3 driver/ddr/fsl: Revise workaround A008511 for A009803 by York Sun · 8 years ago
  53. 7c72578 driver/ddr/fsl: Add more debug registers by York Sun · 8 years ago
  54. e3cef9f driver/ddr/fsl: Fix timing_cfg_2 by York Sun · 8 years ago
  55. 8d56db9 Various, unrelated tree-wide typo fixes. by Robert P. J. Day · 8 years ago
  56. 4be68d0 driver/ddr/fsl: Check condition for erratum A-009803 by Shengzhou Liu · 9 years ago
  57. 2a77a12 drivers/ddr/fsl: Disabling data init if ECC is not enabled by York Sun · 9 years ago
  58. 3abd16b drivers/ddr/fsl: Fix timing_cfg_2 register by York Sun · 9 years ago
  59. 3b33dd2 drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl by Shengzhou Liu · 9 years ago
  60. c4a11bc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · 9 years ago
  61. 31fdba2 arm: mvebu: a38x: Weed out floating point use by Marek Vasut · 9 years ago
  62. c72d12e driver/ddr/fsl: Add workaround for erratum A-010165 by Shengzhou Liu · 9 years ago
  63. 9c3cdc2 driver/ddr/fsl: Add workaround for erratum A-009801 by Shengzhou Liu · 9 years ago
  64. b2dee26 drivers/ddr/fsl: update workaround for erratum A-008511 by Shengzhou Liu · 9 years ago
  65. edfdb99 Fix spelling of "occurred". by Vagrant Cascadian · 9 years ago
  66. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · 9 years ago
  67. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · 9 years ago
  68. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · 9 years ago
  69. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · 9 years ago
  70. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · 9 years ago
  71. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · 9 years ago
  72. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · 9 years ago
  73. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · 9 years ago
  74. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · 9 years ago
  75. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · 9 years ago
  76. 0137e60 Fix typo choosen in comments and printf logs by Alexander Merkle · 9 years ago
  77. 5b2c16a arm: mvebu: Fix ddr3_init() cpu config by Dirk Eibach · 9 years ago
  78. b03e1b1 driver/ddr/fsl: Add workaround for erratum A-009803 by Shengzhou Liu · 9 years ago
  79. 5219944 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete by Shengzhou Liu · 9 years ago
  80. 7557405 Use correct spelling of "U-Boot" by Bin Meng · 9 years ago
  81. e80d11f drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. by Purna Chandra Mandal · 9 years ago
  82. 7ae7a0e drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers by Ed Swarthout · 9 years ago
  83. bdda96c driver/ddr/fsl: Add workaround for A009663 by Shengzhou Liu · 9 years ago
  84. fa2e2fb fsl/ddr: Add workaround for ERRATUM_A009942 by Shengzhou Liu · 9 years ago
  85. e237880 Add more SPDX-License-Identifier tags by Tom Rini · 9 years ago
  86. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · 9 years ago
  87. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · 9 years ago
  88. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · 9 years ago
  89. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · 9 years ago
  90. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · 9 years ago
  91. fae8805 move erratum a008336 and a008514 to soc specific file by Yao Yuan · 9 years ago
  92. 5a46e43 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs by Shengzhou Liu · 9 years ago
  93. 77594b3 driver/ddr/fsl: Update timing config for heavy load by York Sun · 9 years ago
  94. 780ae3d driver/ddr/fsl: Update workaround for A008511 for vref range by York Sun · 9 years ago
  95. d192126 driver/ddr/fsl: Update MR5 RTT park by York Sun · 9 years ago
  96. d4d97ef driver/ddr/fsl: Update DDR4 MR6 for Vref range by York Sun · 9 years ago
  97. 5cb12f6 driver/ddr/fsl: Update DDR4 RTT values by York Sun · 9 years ago
  98. 68c19d7 drivers/ddr/fsl: Fix typo in BIST test for DDR4 by York Sun · 9 years ago
  99. d957a67 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · 9 years ago
  100. 77f7ded armv8: ls2085a: Add support of LS2085A SoC by Prabhakar Kushwaha · 9 years ago