| commit | 3ea5951907ac67c2148ee110d0cd8783167bee7f | [log] [tgz] |
|---|---|---|
| author | Chin Liang See <clsee@altera.com> | Wed Sep 21 10:25:56 2016 +0800 |
| committer | Marek Vasut <marex@denx.de> | Thu Oct 27 08:03:07 2016 +0200 |
| tree | 35830c1c2691e0a2058793a03ee78fc932d92229 | |
| parent | 719ad57c883bae4d87c9717cdcf5c7816a860764 [diff] |
ddr: altera: Configuring SDRAM extra cycles timing parameters To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>