Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b2ccd1cf71c2cec646525adb5025bde8206dbab9 / arch / riscv / cpu / ax25
  1. b2ccd1c riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:49 2023 +0800
  2. 82f0f53 riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() by Yu Chien Peter Lin · Mon Feb 06 16:10:47 2023 +0800
  3. 816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
  4. 08537f3 riscv: ax25: bypass malloc when spl fit boots from ram by Rick Chen · Wed Jan 04 09:55:43 2023 +0800
  5. c1ec25e riscv: ae350: Enable CCTL_SUEN by Rick Chen · Tue Jan 03 16:17:13 2023 +0800
  6. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  7. 2795bf2 riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · Thu Sep 23 10:34:29 2021 +0800
  8. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  9. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
  10. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  11. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  12. d12b55b riscv: ax25: cache: Remove SPL_RISCV_MMODE config check by Pragnesh Patel · Sat Mar 14 19:12:28 2020 +0530
  13. 883275d riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL by Rick Chen · Thu Nov 14 13:52:25 2019 +0800
  14. 276292a riscv: ax25: add SPL support by Rick Chen · Thu Nov 14 13:52:21 2019 +0800
  15. 6333448 common: Move ARM cache operations out of common.h by Simon Glass · Thu Nov 14 12:57:39 2019 -0700
  16. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · Thu Nov 14 12:57:37 2019 -0700
  17. 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · Wed Aug 28 18:46:11 2019 +0800
  18. 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · Wed Aug 28 18:46:09 2019 +0800
  19. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · Thu Aug 29 10:30:13 2019 +0800
  20. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  21. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  22. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
  23. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
  24. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · Fri Jan 04 01:37:29 2019 +0100
  25. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
  26. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  27. de8d80e riscv: Move do_reset() to a common place by Bin Meng · Wed Sep 26 06:55:22 2018 -0700
  28. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700
  29. a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · Wed Sep 26 06:55:11 2018 -0700
  30. b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · Mon Aug 20 14:25:49 2018 +0200
  31. 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · Tue Jun 12 07:48:37 2018 +0200
  32. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800