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git01.mediatek.com / filogic / uboot / b2ccd1cf71c2cec646525adb5025bde8206dbab9 / arch / riscv
  1. b2ccd1c riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:49 2023 +0800
  2. 5cc6b3f riscv: ae350: dts: Update L2 cache compatible string by Yu Chien Peter Lin · Mon Feb 06 16:10:48 2023 +0800
  3. 82f0f53 riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() by Yu Chien Peter Lin · Mon Feb 06 16:10:47 2023 +0800
  4. 816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
  5. 52d54e1 riscv: global_data.h: Correct the comment for PLICSW by Yu Chien Peter Lin · Mon Feb 06 10:06:29 2023 +0800
  6. ae7ed57 Correct SPL uses of LMB by Simon Glass · Sun Feb 05 15:40:13 2023 -0700
  7. 718e569 riscv: memcpy: check src and dst before copy by Rick Chen · Wed Jan 04 09:56:28 2023 +0800
  8. 08537f3 riscv: ax25: bypass malloc when spl fit boots from ram by Rick Chen · Wed Jan 04 09:55:43 2023 +0800
  9. c1ec25e riscv: ae350: Enable CCTL_SUEN by Rick Chen · Tue Jan 03 16:17:13 2023 +0800
  10. c9382b1 riscv: cpu: check U-Mode before counteren write by Nikita Shubin · Wed Dec 14 08:58:43 2022 +0300
  11. 364d002 global: Finish CONFIG -> CFG migration by Tom Rini · Tue Jan 10 11:19:45 2023 -0500
  12. a6b1b3b Merge branch 'next' by Tom Rini · Mon Jan 09 11:30:08 2023 -0500
  13. e84ab96 efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE by Heinrich Schuchardt · Fri Dec 23 02:16:03 2022 +0100
  14. 572c718 Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig by Tom Rini · Fri Dec 02 16:42:44 2022 -0500
  15. c86cb4a arch/riscv: add semihosting support for RISC-V by Kautuk Consul · Wed Dec 07 17:12:35 2022 +0530
  16. 693baee riscv: clarify meaning of CONFIG_SBI_V02 by Heinrich Schuchardt · Tue Nov 08 15:53:12 2022 +0100
  17. a35afb8 riscv: Fix detecting FPU support in standard extension by Yu Chien Peter Lin · Sat Nov 05 14:02:14 2022 +0800
  18. e828edd riscv: dts: fix the mpfs's reference clock frequency by Conor Dooley · Tue Oct 25 08:58:49 2022 +0100
  19. da2a6d0 riscv: dts: Add QSPI NAND device node by Padmarao Begari · Thu Oct 27 11:32:00 2022 +0530
  20. c66a3b2 riscv: dts: Update memory configuration by Padmarao Begari · Thu Oct 27 11:31:59 2022 +0530
  21. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  22. 72cc538 Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE by Simon Glass · Thu Oct 20 18:22:39 2022 -0600
  23. bcb208b riscv: andes_plic.c: use modified IPI scheme by Yu Chien Peter Lin · Fri Oct 14 15:00:18 2022 +0800
  24. c66c950 riscv: support building double-float modules by Heinrich Schuchardt · Wed Oct 12 14:59:51 2022 +0200
  25. 43e1f93 riscv: Fix build against binutils 2.38 by Alexandre Ghiti · Mon Oct 03 18:07:54 2022 +0200
  26. 2e4938b dm: core: Drop ofnode_is_available() by Simon Glass · Tue Sep 06 20:27:17 2022 -0600
  27. df00afa treewide: Drop bootm_headers_t typedef by Simon Glass · Tue Sep 06 20:26:50 2022 -0600
  28. eff2077 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next by Tom Rini · Mon Sep 26 11:27:30 2022 -0400
  29. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  30. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  31. 4f4f583 board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · Fri Sep 09 17:32:40 2022 +0200
  32. ebe3b23 riscv: dts: sifive: Synchronize FU740 and Unmatched DT by Icenowy Zheng · Thu Aug 25 16:11:19 2022 +0800
  33. 13d7170 dt-bindings: clock: sifive: sync FU740 PRCI clock binding header by Icenowy Zheng · Thu Aug 25 16:11:18 2022 +0800
  34. f781746 riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux by Jessica Clarke · Fri Aug 12 18:50:03 2022 +0100
  35. 4150eec riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · Wed Jun 01 10:01:49 2022 +0800
  36. 66ae7fe riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · Fri May 20 14:41:17 2022 +0300
  37. 8aaae3d zynqmp: Run board_get_usable_ram_top() only on main U-Boot by Ashok Reddy Soma · Thu Jul 07 10:45:37 2022 +0200
  38. c65d29f arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED by Michal Simek · Thu Jul 07 10:47:16 2022 +0200
  39. 94b4fec Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig by Tom Rini · Sat Jun 25 11:02:46 2022 -0400
  40. 5a9095c linker_lists: Rename sections to remove . prefix by Andrew Scull · Mon May 30 10:00:04 2022 +0000
  41. 4ddbade Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · Wed May 25 12:16:03 2022 -0400
  42. 53a442a riscv: Clean up asm/io.h by Leo Yu-Chi Liang · Thu May 19 16:43:31 2022 +0800
  43. 7a35171 riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h by Michal Simek · Wed May 18 12:54:01 2022 +0200
  44. ea14390 riscv: alloc space exhausted by Heinrich Schuchardt · Tue Apr 05 16:47:15 2022 +0200
  45. f4b4d75 riscv: provide missing base extension functions by Heinrich Schuchardt · Thu Mar 17 07:36:14 2022 +0100
  46. 295e1ce cmd: sbi: add Performance Monitoring Unit Extension by Heinrich Schuchardt · Wed Mar 16 21:21:18 2022 +0100
  47. 9442f15 Merge tag 'v2022.04-rc5' into next by Tom Rini · Mon Mar 28 12:36:49 2022 -0400
  48. 5b845a4 k210: dts: align plic node with Linux by Niklas Cassel · Tue Mar 01 10:35:42 2022 +0000
  49. b2c0bb4 k210: dts: align fpioa node with Linux by Damien Le Moal · Tue Mar 01 10:35:41 2022 +0000
  50. 0a876d7 k210: dts: add missing power bus clocks by Damien Le Moal · Tue Mar 01 10:35:40 2022 +0000
  51. 6e5a8b7 k210: use the board vendor name rather than the marketing name by Damien Le Moal · Tue Mar 01 10:35:39 2022 +0000
  52. fc55736 event: Convert arch_cpu_init_dm() to use events by Simon Glass · Fri Mar 04 08:43:05 2022 -0700
  53. c8481ef dts: automatically build necessary .dtb files by Rasmus Villemoes · Mon Jan 10 14:34:41 2022 +0100
  54. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  55. f263479 efi_loader: fix SectionAlignment, FileAlignment by Heinrich Schuchardt · Fri Jan 14 21:40:15 2022 +0100
  56. f0106d4 riscv: revert Complete efi header for RV32/64 by Heinrich Schuchardt · Sun Jan 09 18:16:11 2022 +0100
  57. bd07fb4 riscv: qemu: Split devicetree files for qemu_riscv32/64 by Simon Glass · Thu Dec 16 20:59:12 2021 -0700
  58. 9b9c4d5 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · Wed Nov 24 14:32:10 2021 -0800
  59. f50fad6 riscv: Support booting SiFive Unmatched from SPI. by Thomas Skibo · Wed Nov 24 14:32:09 2021 -0800
  60. b56e2fd riscv: dts: Split Microchip device tree by Padmarao Begari · Wed Nov 17 18:21:17 2021 +0530
  61. 2f5b807 riscv: add #define in asm/io.h for some device drivers by Wei Fu · Sun Oct 24 00:31:12 2021 +0800
  62. 69c681e riscv: function to retrieve SBI implementation version by Heinrich Schuchardt · Mon Oct 25 15:09:34 2021 +0200
  63. 579f12b riscv: Avoid io read/write cause wrong result by Nick Hu · Mon Oct 18 11:50:05 2021 +0800
  64. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  65. bedc439 fdtdec: Support reserved-memory flags by Thierry Reding · Fri Sep 03 15:16:21 2021 +0200
  66. 5e33691 fdtdec: Support compatible string list for reserved memory by Thierry Reding · Fri Sep 03 15:16:19 2021 +0200
  67. 85c057e image: Drop IMAGE_ENABLE_OF_LIBFDT by Simon Glass · Sat Sep 25 19:43:21 2021 -0600
  68. 2795bf2 riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · Thu Sep 23 10:34:29 2021 +0800
  69. cc382ff sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · Sun Sep 12 21:11:46 2021 +0200
  70. 2d1c651 riscv: add missing SBI extension definitions by Heinrich Schuchardt · Sun Sep 12 21:11:44 2021 +0200
  71. c7ad952 riscv: Fix setting no-map in reserved memory nodes by Samuel Holland · Sun Sep 12 11:05:47 2021 -0500
  72. 637fa28 lmb: riscv: Add arch_lmb_reserve() by Marek Vasut · Fri Sep 10 22:47:15 2021 +0200
  73. 17a2907 Merge tag 'v2021.10-rc4' into next by Tom Rini · Thu Sep 16 10:29:40 2021 -0400
  74. b28d6b9 riscv: lib: modify the indent by Zong Li · Wed Sep 01 15:01:43 2021 +0800
  75. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  76. c39544c riscv: lib: implement enable_caches for sifive cache by Zong Li · Wed Sep 01 15:01:41 2021 +0800
  77. a33070c common: board_r: support enable_caches for RISC-V by Zong Li · Wed Sep 01 15:01:40 2021 +0800
  78. 79c6855 riscv: show code leading to exception by Heinrich Schuchardt · Sat Sep 04 10:36:49 2021 +0200
  79. 4b198e3 Kconfig: Remove all default n/no options by Michal Simek · Fri Aug 27 08:48:10 2021 +0200
  80. 3ef67ae Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig by Tom Rini · Thu Aug 26 11:47:59 2021 -0400
  81. f1ac8fa riscv: cpu: fu740: Fix typo of date by Zong Li · Mon Aug 02 15:34:14 2021 +0800
  82. 5629aaa efi_loader: add Linux magic to RISC-V crt0 by Heinrich Schuchardt · Fri May 28 22:24:37 2021 +0200
  83. bccfc2e i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · Sat Jul 10 21:14:36 2021 -0600
  84. 288ad1f board: sifive: drop stuff related to unmatched revision 1 by Zong Li · Tue Jul 20 14:26:08 2021 +0800
  85. 51744fe riscv: booti: do not force relocation if force_reloc is not set by Vitaly Wool · Tue Apr 06 10:50:16 2021 +0300
  86. babf1cb riscv: dts: add OpenPiton RISC-V board dts support by Tianrui Wei · Wed Jul 07 15:48:22 2021 +0800
  87. bab770a riscv: dts: add dts for unmatched rev1 by Zong Li · Wed Jun 30 23:23:49 2021 +0800
  88. dab3e8e board: sifive: Add an interface to get PCB revision by Zong Li · Wed Jun 30 23:23:48 2021 +0800
  89. 9627a8e riscv: sifive: fu740: Support i2c in spl by Zong Li · Wed Jun 30 23:23:47 2021 +0800
  90. 3376055 riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · Wed Jun 30 23:23:46 2021 +0800
  91. 2ef594d board: riscv: add openpiton-riscv64 SoC support by Tianrui Wei · Thu Jul 01 12:54:19 2021 +0800
  92. d3e8b73 Merge tag 'v2021.07-rc5' into next by Tom Rini · Mon Jun 28 16:22:13 2021 -0400
  93. e6638b4 k210: dts: Set PLL1 to the same rate as PLL0 by Sean Anderson · Fri Jun 11 00:16:15 2021 -0400
  94. b6ec26b riscv: andes_plic: Fix riscv_get_ipi() mask by Bin Meng · Tue Jun 15 13:45:57 2021 +0800
  95. 2114b47 riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config by Bin Meng · Fri Jun 04 13:51:13 2021 +0800
  96. 85741a2 riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit by Bin Meng · Fri Jun 04 13:51:12 2021 +0800
  97. cd00421 riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes by Bin Meng · Fri Jun 04 13:51:11 2021 +0800
  98. 996068b riscv: ae350: dts: Remove the unnecessary space in bootargs by Bin Meng · Fri Jun 04 13:51:10 2021 +0800
  99. c907594 riscv: ae350: dts: Add SPDX license header by Bin Meng · Fri Jun 04 13:51:09 2021 +0800
  100. 26190b8 riscv: cpu: fu740: clear feature disable CSR by Green Wan · Thu May 27 06:52:14 2021 -0700