| commit | f71410a0ebc26fead9929340ff011a56b79e1669 | [log] [tgz] |
|---|---|---|
| author | Rick Chen <rick@andestech.com> | Tue Apr 02 15:56:42 2019 +0800 |
| committer | Andes <uboot@andestech.com> | Mon Apr 08 09:45:08 2019 +0800 |
| tree | 53f9e29c4d779504b36dbee95bee7f1f44813f4a | |
| parent | 14a107584858150ba40f25de8d6ed59e35a4e63e [diff] |
riscv: ax25: Andes specific cache shall only support in M-mode Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>